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2013 IEEE International Test Conference (ITC) (1999)
Atlantic City, NJ
Sept. 28, 1999 to Sept. 30, 1999
ISSN: 1089-3539
ISBN: 0-7803-5753-1
TABLE OF CONTENTS

Author Index (PDF)

pp. 1162
Session 1: Plenary

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pp. null
Session 2: MCM & Known -Good-Die Testing

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pp. null

A Probe Scheduling Algorithm for MCM Substrates (Abstract)

Se Hyun Park , Andong National University, South Korea
Bruce C. Kim , Michigan State University
Pinshan Jiang , Michigan State University
pp. 31

Testing An MCM For High-Energy Physics Experiments: A Case Study (Abstract)

Silvia Chiusano , Politecnico di Torino
Riccardo Mariani , Caen Microelettronica
Simone Giovannetti , Caen Microelettronica
Paolo Prinetto , Politecnico di Torino
Silvano Motto , Caen Microelettronica
Alfredo Benso , Politecnico di Torino
pp. 38
Session 3: Dynamic Current Testing

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pp. null

Transient Current Testing of 0.25 ?m CMOS Devices (Abstract)

Peter Janssen , Philips Semiconductors
Bram Kruseman , Philips Research Laboratories
Victor Zieren , Philips Research Laboratories
pp. 47

Statistical Threshold Formulation For Dynamic I<sub>dd</sub> Test (Abstract)

Wanli Jiang , Guidant Corporation
Bapiraju Vinnakota , University of Minnesota, Minneapolis
pp. 57

Defect Detection using Power Supply Transient Signal Analysis (Abstract)

James F. Plusquellic , University of Maryland, Baltimore County
Fidel Muradali , Hewlett Packard, Palo Alto
Zheng Yan , University of Maryland, Baltimore County
Amy Germida , University of Maryland, Baltimore County
pp. 67
Session 4: Low Power And Diagnosis in Bist

null (PDF)

pp. null

Minimized Power Consumption For Scan-Based Bist (Abstract)

Hans-Joachim Wunderlich , University of Stuttgart
Stefan Gerstend?rfer , University of Stuttgart
pp. 77

LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation (Abstract)

Sandeep K. Gupta , University of Southern California
Seongmoon Wang , 3Dfx Interactive
pp. 85

Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information (Abstract)

Nur A. Touba , University of Texas, Austin
Jayabrata Ghosh-Dastidar , University of Texas, Austin
Debaleena Das , University of Texas, Austin
pp. 95
Session 5: Volume Production Testing

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pp. null

Expediting Ramp-to-Volume Production (Abstract)

Jason Parker , Texas Instruments
Gordon Gammie , Texas Instruments
Sri Jandhyala , Texas Instruments
John Olson , Texas Instruments
Craig Force , Texas Instruments
Hari Balachandran , Texas Instruments
Kenneth M. Butler , Texas Instruments
pp. 103

Test Process Optimization: Closing The Gap In The Defect Spectrum (Abstract)

Simon Martin , Motorola Ireland Ltd.
Chryssa Dislis , Motorola Ireland Ltd.
Norma Barrett , Motorola Ireland Ltd.
pp. 124
Session 6: Microprocessor Testing

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pp. null

DFT Advances in Motorola?s MPC7400, a PowerPC<sup>TM</sup> Microprocessor (Abstract)

Carol Pyron , Motorola, Inc.
James Golab , Motorola, Inc.
Bruce Long , Motorola, Inc.
Mike Alexander , Motorola, Inc.
Nandu Tendolkar , Motorola, Inc.
George Joos , Motorola, Inc.
Robert Molyneaux , Motorola, Inc.
Rajesh Raina , Motorola, Inc.
pp. 137
Session 7: Board Test-Lecture Series

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pp. null

Breaking The Complexity Spiral In Board Test (Abstract)

Stephen F. Scheiber , ConsuLogic Consulting Services
pp. 155

Using LSSD to Test Modules at the Board Level (Abstract)

Thomas A. Ziaja , IBM Corp. Austin, Texas
pp. 163
Session 8: Delay Testing

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pp. null

Delay Testing Considering Power Supply Noise Effects (Abstract)

Angela Krstic , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Yi-Min Jiang , University of California, Santa Barbara
pp. 181

Test Generation for Crosstalk-Induced Delay in Integrated Circuits (Abstract)

Wei-Yu Chen , University of Southern California
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 191

Accurate Path Delay Fault Coverage is Feasible (Abstract)

S. Tragoudas , The University of Arizona
pp. 201
Session 9: Analog Test Methods

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pp. null

A New Approach to RF Impedance Test (Abstract)

Dino Ren Tao , LTX Asia International, Inc.
pp. 216

Subband Filtering Scheme for Analog and Mixed-Signal Circuit Testing (Abstract)

Jeongjin Roh , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
pp. 221

Speed-up of High Accurate Analog Test Stimulus Optimization (Abstract)

Abdelhakim Khouas , Universit? Pierre et Marie Curie
Anne Derieux , Universit? Pierre et Marie Curie
pp. 230
Session 10: Virtual And Real Test Software

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pp. null

Automatic Timing Margin Failure Location Analysis by CycleStretch Method (Abstract)

Mitsuo Matsumoto , ADVANTEST Corporation
Yoshiharu Ikeda , Hitachi ULSI Systems Co., Ltd.
pp. 245

Design for In-System Programming (Abstract)

David A. Bonnett , ASSET InterTech, Inc.
pp. 252
Session 11: DFT

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pp. null

Robust Testability of Primitive Faults using Test Points (Abstract)

Prem R. Menon , University of Massachusetts
Ramesh C. Tekumalla , Intel Corporation
pp. 260

Delay Testing of SOI Circuits: Challenges with the History Effect (Abstract)

Eric MacDonald , Advanced PowerPC Development
Nur A. Touba , University of Texas, Austin
pp. 269

A DFT Technique for High Performance Circuit Testing (Abstract)

Mansour Shashaani , University of Waterloo
Manoj Sachdev , University of Waterloo
pp. 276

Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element (Abstract)

Egor S. Sogomonyan , Russian Academy of Sciences
Michael G?ssel , University of Potsdam
Markus Seuring , University of Potsdam
Adit D. Singh , Auburn University
pp. 286
Session 12: Embedded Memories

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pp. null
Session 13: MEMS Fault Modeling & Test

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pp. null

Fault modeling of suspended thermal MEMS (Abstract)

S. Mir , TIMA Laboratory
M. Lubaszewski , TIMA Laboratory
B. Courtois , TIMA Laboratory
E.F. Cota , TIMA Laboratory
B. Charlot , TIMA Laboratory
pp. 319

Particulate Failures for Surface-Micromachined MEMS (Abstract)

R. D. (Shawn) Blanton , Carnegie Mellon University
Tao Jiang , Carnegie Mellon University
pp. 329

IMEMS Accelerometer Testing - Test Laboratory Development and Usage (Abstract)

Robert W. Brocato , Sandia National Laboratories
Richard W. Beegle , Sandia National Laboratories
Ronald W. Grant , Sandia National Laboratories
pp. 338
Session 14: Industrial Applications of Bist

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pp. null

Low Overhead Test Point Insertion For Scan-Based BIST (Abstract)

Michinobu Nakao , Hitachi, Ltd.
Kazuhiko Iijima , Hitachi, Ltd.
Kazumi Hatayama , Hitachi, Ltd.
Seiji Terada , Hitachi Business Solution, Ltd.
Seiji Kobayashi , Hitachi, Ltd.
pp. 348

Logic BIST for Large Industrial Designs: Real Issues and Case Studies (Abstract)

Abu Hassan , Mentor Graphics Corporation
Mark Kassab , Mentor Graphics Corporation
Nagesh Tamarapalli , Mentor Graphics Corporation
Janusz Rajski , Mentor Graphics Corporation
Graham Hetherington , Texas Instruments, Ltd.
Tony Fryars , Texas Instruments, Ltd.
pp. 358

Synthesis of Pattern Generators Based on Cellular Automata with Phase Shifters (Abstract)

Jerzy Tyszer , Poznan University of Technology
Janusz Rajski , Mentor Graphics Corporation
Grzegorz Mrugalski , Poznan University of Technology
pp. 368
Session 15: Production Wafer Test: Where the Probes Meet The Pads

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pp. null

Characterization and Optimization of the Production Probing Process (Abstract)

Rich Samuelson , Hewlett-Packard Company
David Shaw , Hewlett-Packard Company
Minh Quach , Hewlett-Packard Company
pp. 378

Probe Contact Resistance Variations During Elevated Temperature Wafer Test (Abstract)

Reynaldo M. Rincon , Texas Instruments Corporation
Jerry J. Broz , Advanced Probing Systems, Inc.
pp. 396
Session 16: Design Validation & Analysis for Evolving Technologies

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pp. null

Checking Sequence Generation for Asynchronous Sequential Elements (Abstract)

F. J. Ferguson , University of California; Santa Cruz
S. G?ren , University of California; Santa Cruz
pp. 406

Functional Verification of Intellectual Properties (IP): a Simulation-Based Solution for an Application-Specific Instruction-set Processor (Abstract)

Hubert Kaeslin , Swiss Federal Institute of Technology
Thomas R?wer , Swiss Federal Institute of Technology
Norbert Felber , Swiss Federal Institute of Technology
Wolfgang Fichtner , Swiss Federal Institute of Technology
Manfred Stadler , Swiss Federal Institute of Technology
Markus Thalmann , Siemens Switzerland AG
pp. 414

Critical Path Identification and Delay Tests of Dynamic Circuits (Abstract)

Jacob A. Abraham , The University ofTexas at Austin
Kyung Tek Lee , IBM Austin Research Laboratory
pp. 421
Session 17: Board Test: Interconnect Test

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pp. null

An Embedded Technique For At-Speed Interconnect Testing (Abstract)

Stephen Pateras , LogicVision, Inc.
Jean-Francois Cote , LogicVision Canada, Inc.
Harry Hulvershorn , LogicVision Canada, Inc.
Benoit Nadeau-Dostie , LogicVision Canada, Inc.
pp. 431

Interconnect Delay Fault Testing with IEEE 1149.1 (Abstract)

Paul Soong , Nortel Networks
Yuejian Wu , Nortel Networks
pp. 449
Session 18: Enhanced Test & Diagnosis of IC Process Defects

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pp. null

Correlation of Logical Failures to a Suspect Process Step (Abstract)

Kenneth M. Butler , Texas Instruments
Daniel Shupp , Texas Instruments
Jason Parker , Texas Instruments
Craig Force , Texas Instruments
Hari Balachandran , Texas Instruments
Stephanie Butler , Texas Instruments
Jason Smith , Texas Instruments
pp. 458

Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation (Abstract)

Maurice Lousberg , Philips Research Laboratories
Keith Baker , Philips Research Laboratories
Ivo Schanstra , Philips Semiconductors
Guido Gronthoud , Philips Research Laboratories
Charles Hawkins , University of New Mexico
pp. 467

Optimal Conditions for Boolean and Current Detection of Floating Gate Faults (Abstract)

M. Renovell , LIRMM-UMII
A. Ivanov , University of British Columbia
F. Azais , LIRMM-UMII
S. Rafiq , University of British Columbia
Y. Bertrand , LIRMM-UMII
pp. 477
Session 19: Embedded Core Test

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pp. null

Embedded X86 Testing Methodology (Abstract)

Luis Basto , Advanced Micro Devices
Asif Khan , Advanced Micro Devices
Pete Hodakievic , Advanced Micro Devices
pp. 487

Testing a System-On-a-Chip with Embedded Microprocessor (Abstract)

Rochit Rajsuman , Advantest America R&D Center
pp. 499
Session 20: Issues in Tester Accuracy

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pp. null

Towards a Standardized Procedure for Automatic Test Equipment Timing Accuracy Evaluation (Abstract)

W. R. Ortner , Lucent Technologies - Bell Laboratories
Y. Cai , Lucent Technologies - Bell Laboratories
C. T. Garrenton , Lucent Technologies - Bell Laboratories
pp. 509

The Value of Tester Accuracy (Abstract)

Wajih Dalal , Schlumberger Automated Test Equipment
Song Miao , Schlumberger Automated Test Equipment
pp. 518

An Accurate Simulation Model of the ATE Test Environment for Very High Speed Devices (Abstract)

Jung Cho , Lucent Technologies
Yi Cai , Lucent Technologies
Bill Ortner , Lucent Technologies
pp. 524
Session 21: Mixed-Signal Bist Techniques

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pp. null

BIST for Phase-Locked Loops in Digital Applications (Abstract)

Stephen Sunter , LogicVision, Inc.
Aubin Roy , LogicVision, Inc.
pp. 532

Auto-Calibrating Analog Timer for On-Chip Testing (Abstract)

E. S?nchez-Sinencio , Texas A&M University
B. Provost , Texas A&M University
pp. 541

Effective Oscillation-Based Test for application to a DTMF Filter Bank (Abstract)

Gloria Huertas , University of Sevilla
Adoraci? Rueda , University of Sevilla
Jos? L. Huertas , University of Sevilla
Diego V?zquez , University of Sevilla
pp. 549
Session 22: Board Test: Practice Makes Perfect

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pp. null

Static Component Interconnection Test Technology in Practice (Abstract)

Rob Raaijmakers , Philips Research
Frans de Jong , Philips Research
Steffen Hellmold , Fujitsu Mikroelektronik GmbH, Germany
pp. 556

The HASS Development Process (Abstract)

David Rahe , QualMark Corporation
pp. 566

Limited Access Testing of Analog Circuits: Handling Tolerances (Abstract)

Michael Spears , Hewlett Packard Company, MTD
Cherif Ahrikencheikh , Hewlett Packard Company, MTD
pp. 577
Session 23: Fault Simulation from Bridges to RTL

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pp. null

A Comparison of Bridging Fault Simulation Methods (Abstract)

Imtiaz Shaik , Advanced Micro Devices, Inc.
R. Scott Fetherston , Advanced Micro Devices, Inc.
Siyad Ma , Chameleon Systems, Inc.
pp. 587
Session 24: Practicing Embedded Core Test

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pp. null

Towards a Standard for Embedded Core Test: An Example (Abstract)

Tony Taylor , Fluence
Rohit Kapur , Synopsys
Lee Whetsel , Texas Instruments
Yervant Zorian , LogicVision
Erik Jan Marinissen , Philips Research
pp. 616

Trends in SLI design and their effect on test (Abstract)

Robert Aitken , Hewlett-Packard Co.
Fidel Muradali , Hewlett-Packard Co.
pp. 628

Test Features of a Core-Based Co-Processor Array for Video Applications (Abstract)

Harry van Herten , Philips Research Laboratories
Jos van Beers , Philips Research Laboratories
pp. 638
Session 25: (Panel) Is Analog Fault Simulation A Key to Product Quality? Practical Considerations

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pp. null
Session 26: On-line Testing Techniques

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pp. null

Self-Checking Scheme for Very Fast Clocks? Skew Correction (Abstract)

Mani Soma , D.E.E. University of Washington, Seattle
Flavio Giovanelli , D.E.I.S. University of Bologna
Bruno Ricc? , D.E.I.S. University of Bologna
Cecilia Metra , D.E.I.S. University of Bologna
pp. 652

A Design Diversity Metric and Reliability Analysis for Redundant Systems (Abstract)

Edward J. McCluskey , Stanford University
Nirmal R. Saxena , Stanford University
Subhasish Mitra , Stanford University
pp. 662

Finite State Machine Synthesis with Concurrent Error Detection (Abstract)

Nirmal Saxena , Stanford University
Edward J. McCluskey , Stanford University
Chaohuang Zeng , Stanford University
pp. 672
Session 27: System Test-Lecture Series

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pp. null

The Evolution of a System Test Process (Abstract)

Robert Bleck , Motorola Inc,
Chryssa Dislis , Motorola Ireland Ltd,
Simon Martin , Motorola Ireland Ltd,
Des Farren , Motorola Ireland Ltd,
pp. 680

PC Manufacturing Test in a High Volume Environment (Abstract)

David Williams , Dell Computer Corporation
pp. 698

DFT, Test Lifecycles and the Product Lifecycle (Abstract)

Gordon D Robinson , Credence Systems Corporation
pp. 705
Session 28: Production I<sub>DDQ</sub> Testing Beyond Single-Threshold Measurements

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pp. null

Clustering Based Techniques for I<sub>DDQ</sub> Testing (Abstract)

Hari Balachandran , Texas Instruments Inc.
Anura P. Jayasumana , Colorado State University
Sri Jandhyala , Texas Instruments Inc.
pp. 730

Current Ratios: A Self-Scaling Technique for Production IDDQ Testing (Abstract)

Peter Maxwell , Hewlett-Packard Company
Minh Quach , Hewlett-Packard Company
Pete O'Neill , Hewlett-Packard Company
Neal Jaarsma , Hewlett-Packard Company
Rob Aitken , Hewlett-Packard Company
Don Wiseman , Hewlett-Packard Company
Roland Dudley , Hewlett-Packard Company
pp. 738
Session 29: Testing Analog to Digital Converters

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pp. null
Session 30: Issues in High-Speed Testing

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pp. null

A New Method for Jitter Decomposition Through Its Distribution Tail Fitting (Abstract)

Jan Wilstrup , Wavecrest Corporation
Mike P. Li , Wavecrest Corporation
Dennis Petrich , Wavecrest Corporation
Ross Jessen , Wavecrest Corporation
pp. 788

At-Speed Structural Test (Abstract)

Burnell G. West , Schlumberger ATE
pp. 795

Test Support Processors for Enhanced Testability of High Performance Circuits (Abstract)

D.C. Keezer , Georgia Institute of Technology
Q. Zhou , Georgia Institute of Technology
pp. 801
Session 31: Test Methodology State of Practice & Case Studies

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pp. null

Testability of the Philips 80C51 Micro-controller (Abstract)

J.Th. van der Linden , Delft University of Technology
M.H. Konijnenburg , Delft University of Technology
A.J. van de Goor , Delft University of Technology
pp. 820
Session 32: System Test Methods from DFT to End of Life

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pp. null
Session 33: Design for Diagnostics

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pp. null

The Attack of the "Holey Shmoos": A Case Study of Advanced DFD and Picosecond Imaging Circuit Analysis (PICA) (Abstract)

Daniel Knebel , IBM T.J. Watson Research
Stanislav Polonsky , IBM T.J. Watson Research
Dennis Manzer , IBM T.J. Watson Research
Moyra McManus , IBM T.J. Watson Research
Pia Sanda , IBM T.J. Watson Research
Steven Steen , IBM T.J. Watson Research
Yuen Chan , IBM
pp. 883

Silicon Debug: Scan Chains Alone Are Not Enough (Abstract)

Gert Jan van Rootselaar , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
pp. 892
Session 34: Test Synthesis

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pp. null

A High-Level BIST Synthesis Method Based on a Region-wise Heuristic for an Integer Linear Programming (Abstract)

Han Bin Kim , Virginia Polytechnic Institute and State University
Dong Sam Ha , Virginia Polytechnic Institute and State University
pp. 903
Session 35: Mixed-Signal ATE Issues & Optical Probing

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pp. null

Practical Optical Waveform Probing of Flip-Chip CMOS Devices (Abstract)

William K. Lo , Schlumberger Test and Transactions
Kenneth R. Wilsher , Schlumberger Test and Transactions
pp. 932

A Method to Improve the Performance of High-speed Waveform Digitizing (Abstract)

Koji Asami , ADVANTEST Corporation
Shinsuke Tajiri , ADVANTEST Corporation
pp. 947
Session 36: On-line Testing for FPGAS and Processors

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pp. null

On-Line Fault Detection In DSP Circuits Using Extrapolated Checksums with Minimal Test Points (Abstract)

Sudip Chakrabarti , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 955

An Efficient On-line-Test and Back-up Scheme for Embedded Processors (Abstract)

F. Pompsch , Brandenburg Technical University at Cottbus, Germany
M. Pflanz , Brandenburg Technical University at Cottbus, Germany
H.T. Vierhaus , Brandenburg Technical University at Cottbus, Germany
pp. 964

Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications (Abstract)

Miron Abramovici , Lucent Technologies
Charles Stroud , University of Kentucky
Sajitha Wijesuriya , Lucent Technologies
Vinay Verma , Univ. of Illinois at Chicago
Carter Hamilton , University of Kentucky
pp. 973
Session 37: Memory Testing

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pp. null

Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs (Abstract)

Ad J. van de Goor , Delft University of Technology
Ivo Schanstra , Philips Semiconductors MOS4YOU
pp. 983

An On-Line BISTed SRAM IP Core (Abstract)

Alessio Pricco , Italtel S.p.A.
Monica Lobetti-Bondoni , Italtel S.p.A.
Alfredo Benso , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
pp. 993

Port Interference Faults in Two-Port Memories (Abstract)

A. J. van de Goor , Delft University of Technology
Said Hamdioui , Intel Corporation; Delft University of Technology
pp. 1001
Session 38: Test Generation

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pp. null

Using Verilog Simulation Libraries for ATPG (Abstract)

Peter Wohl , Synopsys Inc.
John Waicukauski , Synopsys Inc.
pp. 1011

STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs (Abstract)

R. Tompson , Mentor Graphics Corporation
K.-H. Tsai , Mentor Graphics Corporation
J. Rajski , Mentor Graphics Corporation
M. Marek-Sadowska , Univ. of California, Santa Barbara
pp. 1021

Modeling the Probability of Defect Excitation for a Commercial IC with Implications for Stuck-at Fault-Based ATPG Strategies (Abstract)

M. Ray Mercer , Texas A&M University
Jennifer Dworak , Texas A&M University
Michael R. Grimaila , Texas A&M University
Li-C. Wang , Texas A&M University
Sooryong Lee , Texas A&M University
pp. 1031
Session 39: Advanced Solutions for SOC Test

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pp. null

HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs (Abstract)

Alfredo Benso , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
Silvia Cataldo , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Yervant Zorian , Logic Vision
pp. 1038

Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling (Abstract)

Hyungwon Kim , University of Michigan, Ann Arbor
John P. Hayes , University of Michigan, Ann Arbor
pp. 1045
Session 40: Applying Diagnosis in A Production Test Environment

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pp. null

Eliminating the Ouija? Board: Automatic Thresholds and Probabilistic I<sub>DDQ</sub> Diagnosis (Abstract)

Tracy Larrabee , University of California, Santa Cruz
David B. Lavo , University of California, Santa Cruz
Jonathon E. Colburn , University of California, Santa Cruz
pp. 1065

Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor (Abstract)

Dan Knebel , IBM T.J. Watson Research
Franco Motika , IBM/MiCRUS
Moyra McManus , IBM T.J. Watson Research
Julie Lee , IBM
pp. 1073

The Effects of Test Compaction on Fault Diagnosis (Abstract)

Ruifeng Guo , University of Iowa
Irith Pomeranz , University of Iowa
Sudhakar M. Reddy , University of Iowa
Yun Shao , University of Iowa
pp. 1083
Session 41: Time-to-Market: Lecture Series

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pp. null

Is DFT Right for You? (Abstract)

Jim Johnson , Motorola Corporation, Austin TX
pp. 1090

Design for Test and Time to Market -- Friends or Foes (Abstract)

Jon Turino , SynTest Technologies, Inc.
pp. 1098
Panel 1: High Time for High-Level ATPG

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pp. null

High Time for High Level ATPG (PDF)

Wu-Tung Cheng , Mentor Graphics Corporation
pp. 1113

Changing our Path to High Level ATPG (PDF)

Scott Davidson , Sun Microsystems Inc.
pp. 1114

High Time for Higher Level BIST (PDF)

Chris Papchristou , Case Western Reserve University
pp. 1117
Panel 2: Production Memory Tester-Present And Future

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pp. null
Panel 3: SIA Roadmaps: Sunset Boulevard For I<sub>DDQ</sub>

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pp. null
Panel 4: Thin Gate Oxide Reliability

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pp. null

Applying Lessons Learned From TDDB Testing (PDF)

James Prendergast , Institute Of Technology Tralee, Clash, Tralee Co. Kerry, Ireland; Raheen Industrial Estate, Limerick, Ireland
pp. 1123
Panel 5: What Do We Need System Test For?

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pp. null
Panel 6: ITC'99 Benchmark Circuits-Preliminary Results

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pp. null

Benchmarking DAT with the ITC?99 ATPG Benchmarks (PDF)

Hans van der Linden , Delft University of Technology
Mario Konijnentmrgl , Delft University of Technology
Jeroen Geuzebroek , Delft University of Technology
pp. 1127

Automatic Functional Test Generation - A Reality (PDF)

Raghuram S. Tupuri , Texas Microprocessor Division
pp. 1130
Panel 7: Increasing Test Coverage in a VLSI Design

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pp. null

VLSI Design 101 - The Test Module (PDF)

John Harrington , Lucent Technologies
pp. 1134
Panel 8: SCITT: Back to Basics in Mass Production Testing

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pp. null
Panel 9: DFT is All I Can Afford, Who Cares About Design for Yield or Design for Reliability!

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pp. null

DFT, DFY, DFR: Who Cares? (PDF)

Scott Fetherston , Advanced Micro Devices
pp. 1144
Panel 10: Output in STIL, Input in STIL

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pp. null

Is there a STIL for Mixed Signal Testing? (PDF)

Marc Loranger , Credence Systems Corporation
pp. 1151
1998 ITC Best Paper:

1998 ITC Best Paper: Failure Analysis of Timing and I<sub>DDQ</sub>-only Failures from the SEMATECH Test Methods Experiment (Abstract)

Jason Wright , IBM Microelectronics
Donato Forlenza , Micrus Corporation
Atul Patel , IBM Microelectronics
Phil Nigh , IBM Microelectronics
Dave Vallett , IBM Microelectronics
Ray Kurtulik , Micrus Corporation
Wendy Chong , Micrus Corporation
Franco Motika , Micrus Corporation
pp. 1152
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