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International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)
Atlantic City, NJ
Sept. 28, 1999 to Sept. 30, 1999
ISSN: 1089-3539
ISBN: 0-7803-5753-1
pp: 1038
Alfredo Benso , Politecnico di Torino
Silvia Cataldo , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Yervant Zorian , Logic Vision
ABSTRACT
This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation, respectively.
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CITATION

A. Benso, S. Chiusano, S. Cataldo, P. Prinetto and Y. Zorian, "HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs," International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)(ITC), Atlantic City, NJ, 1999, pp. 1038.
doi:10.1109/TEST.1999.805837
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