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International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) (1999)
Atlantic City, NJ
Sept. 28, 1999 to Sept. 30, 1999
ISSN: 1089-3539
ISBN: 0-7803-5753-1
pp: 993
Monica Lobetti-Bondoni , Italtel S.p.A.
Alessio Pricco , Italtel S.p.A.
Alfredo Benso , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
ABSTRACT
In digital systems design, strict reliability constraints usually impose very low fault latency and high degree of fault detection of permanent and transient faults. In particular, memory modules, as either devices or IP cores, appeared as one of the most critical parts. This paper presents an advanced on-line memory BIST architecture implemented as an IP core developed for telecommunication applications at Italtel SpA, the major Italian manufacturers of telecom systems. A fault latency reduction architecture, a code-based fault detection scheme, and an architecture-based fault avoidance have been composed to meet the required reliability constraints.
INDEX TERMS
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CITATION

A. Pricco, M. Lobetti-Bondoni, A. Benso, P. Prinetto and S. Chiusano, "An On-Line BISTed SRAM IP Core," International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)(ITC), Atlantic City, NJ, 1999, pp. 993.
doi:10.1109/TEST.1999.805832
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