The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (1998)
Washington, D.C. USA
Oct. 18, 1998 to Oct. 23, 1998
ISSN: 1089-3539
ISBN: 0-7803-5093-6
TABLE OF CONTENTS
INTRODUCTORY SECTION

Reviewers (PDF)

pp. 17

Author Index (PDF)

pp. 1078
SESSION 1: PLENARY
SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES

Failure Analysis of Timing and IDDq-only Failures from the SEMATECH Test Methods Experiment (Abstract)

Phil Nigh , IBM Microelectronics
Atul Patel , IBM Microelectronics
Dave Vallett , IBM Microelectronics
Jason Wright , IBM Microelectronics
pp. 43
SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION

Consequences of Port Restrictions on Testing Two-Port Memories (Abstract)

S. Hamdioui , Delft University of Technology
A. J. van de Goor , Delft University of Technology
pp. 63

A New Framework for Generating Optimal March Tests For Memory Arrays (Abstract)

Kamran Zarrineh , State University of New York at Buffalo
Sreejit Chakravarty , Intel Corporation
Shambhu J. Upadhyaya , State University of New York at Buffalo
pp. 73
SESSION 4: DFT IN PRACTICE

DELAY TEST OF CHIP I/Os USING LSSD BOUNDARY SCAN (Abstract)

Ulrich Baur , IBM System/390 Division
Pamela Gillis , IBM Microelectronics Division
Kevin McCauley , IBM Test Design Automation
Francis Woytowich , IBM Microelectronics Division
pp. 83

Designing for Scan Test of High Performance Embedded Memories (Abstract)

George Joos , Motorola
E. Kofi Vida-Torku , International Business Machines
pp. 101
SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST

MAXIMIZING HANDLER THERMAL THROUGHPUT WITH A RIB-ROUGHENED TEST TRAY (Abstract)

Alexander H. Slocum , Massachusetts Institute of Technology
John H. Lienhard V , Massachusetts Institute of Technology
Andreas C. Pfahnl , Kinetrix, Inc.
pp. 109

TEMPERATURE CONTROL OF A HANDLER TEST INTERFACE (Abstract)

Andreas C. Pfahnl , Kinetrix, Inc.
John H. Lienhard V , Massachusetts Institute of Technology
Alexander H. Slocum , Massachusetts Institute of Technology
pp. 114

A Test Site Thermal Control System for At-Speed Manufacturing Testing (Abstract)

Steve Knostman , Schlumberger Test & Transactions
Tom Jones , Schlumberger Test & Transactions
James Maveety , Intel Corporation
Mark Malinoski , Schlumberger Test & Transactions
pp. 119
SESSION 6: EMBEDDED CORES

Testing Embedded-Core Based System Chips (Abstract)

Sujit Dey , University of California at San Diego
Erik Jan Marinissen , Philips Research
Yervant Zorian , LogicVision
pp. 130
SESSION 7: BIST SYNTHESIS

BETSY: Synthesizing Circuits for a Specified BIST Environment (Abstract)

Zhe Zhao , University of Texas at Austin
Bahram Pouya , University of Texas at Austin and Motorola
Nur A. Touba , University of Texas at Austin
pp. 144

Test Session Oriented Built-in Self-testable Data Path Synthesis (Abstract)

Han Bin Kim , Virginia Polytechnic Institute and State University
Dong Sam Ha , Virginia Polytechnic Institute and State University
Takeshi Takahashi , Advantest America R&D Center Inc.
pp. 154

An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis (Abstract)

Srinivas Devadas , Massachusetts Institute of Technology
Kurt Keutzer , University of California at Berkeley
pp. 164
SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING

Toward Understanding "Iddq-Only" Fails (Abstract)

Anne E. Gattiker , Carnegie Mellon University
Wojciech Maly , Carnegie Mellon University
pp. 174

ANALYSIS OF PATTERN-DEPENDENT AND TIMING-DEPENDENT FAILURES IN AN EXPERIMENTAL TEST CHIP (Abstract)

Chao-Wen Tseng , Stanford University
Jonathan T.-Y. Chang , Stanford University
Edward J. McCluskey , Stanford University
Chien-Mo James Li , Stanford University
Mike Purtell , Advantest America R&D Center, Inc.
pp. 184

CMOS IC Reliability Indicators and Burn-In Economics (Abstract)

Alan W. Righter , Analog Devices
Jerry M. Soden , Sandia Labs
Charles F. Hawkins , University of New Mexico
Peter Maxwell , Hewlett-Packard
pp. 194

Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS ICs (Abstract)

Victor Zieren , Philips Research Laboratories
Peter Janssen , Philips Research Laboratories
Manoj Sachdev , Philips Research Laboratories
pp. 204
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS

A Distributed BIST Technique for Diagnosis of MCM Interconnections (Abstract)

Yervant Zorian , LogicVision, Inc.
Rajesh Pendurkar , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 214

TESTING A MULTICHIP PACKAGE FOR A CONSUMER COMMUNICATIONS APPLICATION (Abstract)

Rodger Schuttert , Philips Electronic Design and Tools
Alex Biewenga , Philips Electronic Design and Tools
Math Muris , Philips Electronic Design and Tools
Urs Fawer , Philips Semiconductors AG
pp. 222

Improved Sensitivity for Parallel Test of Substrate Interconnections (Abstract)

D.C. Keezer , Georgia Institute of Technology
J.S. Davis , Georgia Institute of Technology
K.E. Newman , Georgia Institute of Technology
pp. 228

A High Throughput Test Methodology for MCM Substrates (Abstract)

David Keezer , Georgia Institute of Technology
Bruce C. Kim , Michigan State University
Abhijit Chatterjee , Georgia Institute of Technology
pp. 234
SESSION 10: MIXED-SIGNAL TEST TECHNIQUES

Multi-Output One-Digitizer Measurement (Abstract)

M. Shibata , Asahi Kasei Microsystems Co.
S. Sasho , Asahi Kasei Microsystems Co.
pp. 258
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS

COST OF TEST REDUCTION (Abstract)

Hervé DESHAYES , STMicroelectronics
pp. 265

FINE PITCH (45 MICRON) P4 PROBING (Abstract)

Toshinori Ishii , Mitsubishi Materials Corp.
Hideaki Yoshida , Mitsubishi Materials Corp.
pp. 272
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES

A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores (Abstract)

Robert Arendsen , Philips Semiconductors
Gerard Bos , Philips Semiconductors
Maurice Lousberg , Philips Research Laboratories
Clemens Wouters , Philips Semiconductors
Hans Dingemanse , Philips Semiconductors
Erik Jan Marinissen , Philips Research Laboratories
pp. 284

A Structured Test Re-Use Methodology for Core-Based System Chips (Abstract)

Sandeep Bhatia , Duet Technologies Inc.
Prab Varma , Duet Technologies Inc.
pp. 294

Core Test Connectivity, Communication, & Control (Abstract)

Lee Whetsel , Texas Instruments Inc.
pp. 303

Modular Logic Built-In Self-Test for IP Cores (Abstract)

Jerzy Tyszer , Poznan University of Technology
Janusz Rajski , Mentor Graphics Corporation
pp. 313
SESSION 13: TEST SYNTHESIS

A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits (Abstract)

Y. L. Wu , Chinese University of Hong-Kong
S. C. Chang , National Chung-Cheng University
W. B. Jone , National Chung-Cheng University
J. C. Rau , National Chung-Cheng University
pp. 322

TAO: Regular Expression based High-Level Testability Analysis and Optimization (Abstract)

Ganesh Lakshminarayana , Princeton University
Niraj K. Jha , Princeton University
Srivaths Ravi , Princeton University
pp. 331

A NEW APPROACH TO SCAN CHAIN REORDERING USING PHYSICAL DESIGN INFORMATION (Abstract)

Xinli Gu , Cisco Systems, Inc.
Mokhtar Hirech , Synopsys, Inc.
James Beausang , Synopsys, Inc.
pp. 348
SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES
SESSION 15: BOARD AND SYSTEM TEST

DIGITAL BUS FAULTS MEASURING TECHNIQUES (Abstract)

Reuben Schrift , E&M Engineering (Y.G.R) Ltd.
pp. 382
SESSION 16: RECENT ADVANCES IN BIST

Built-In Self-Test of FPGA Interconnect (Abstract)

Miron Abramovici , Bell Labs - Lucent Technologies
Sajitha Wijesuriya , University of Kentucky
Carter Hamilton , University of Kentucky
Charles Stroud , University of Kentucky
pp. 404

Accumulator Based Deterministic BIST (Abstract)

Rainer Dorsch , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
pp. 412

A BIST Scheme for the Detection of Path-Delay Faults (Abstract)

Tapan J. Chakraborty , Bell Laboratories, Lucent Technologies
Nilanjan Mukherjee , Bell Laboratories, Lucent Technologies
Sudipta Bhawmik , Bell Laboratories, Lucent Technologies
pp. 422
SESSION 17: INTRODUCTION TO MEMS

Microelectromechanical Systems (MEMS) Tutorial (Abstract)

Kaigham J. Gabriel , Carnegie Mellon University
pp. 432

A Performance Analysis System for MEMS using Automated Imaging Methods (Abstract)

Sam L. Miller , Sandia National Laboratories
Glenn F. LaVigne , Sandia National Laboratories
pp. 442
SESSION 18: ADVANCES IN EMBEDDED CORE TEST

Scan Chain Design for Test Time Reduction in Core-Based ICs (Abstract)

Erik Jan Marinissen , Philips Research Laboratories
Joep Aerts , Philips Research Laboratories and Eindhoven University of Technology
pp. 448

A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem (Abstract)

Hiroshi Date , Institute of Systems & Information Technologies/KYUSHU
Makoto Sugihara , Kyushu University
Hiroto Yasuura , Kyushu University
pp. 465
SESSION 19: MICROPROCESSOR TESTING

Diagnostic Techniques for the UltraSPARC™ Microprocessors (Abstract)

Aswin Mehta , Texas Instruments Inc.
Anjali Kinra , Texas Instruments Inc.
Jackie Mitchell , Texas Instruments Inc.
Fred Valente , Texas Instruments Inc.
Neal Smith , Texas Instruments Inc.
pp. 480

Testability Access of the High Speed Test Features in the Alpha 21264 Microprocessor (Abstract)

David R. Akeson , Compaq Computer Corporation
Daniel B. Jackson , Compaq Computer Corporation
Dilip K. Bhavsar , Compaq Computer Corporation
Michael K. Gowan , Compaq Computer Corporation
pp. 487
SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES

A Scalable Architecture for VLSI Test (Abstract)

Ed Chang , Credence Systems Corporation
Jim Seaton , Credence Systems Corporation
David Cheung , Credence Systems Corporation
Gary Smith , Credence Systems Corporation
Robert Huston , Credence Systems Corporation
pp. 500
SESSION 21: CONCURRENT CHECKING

On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults (Abstract)

Cecilia Metra , University of Bologna
Bruno Riccò , University of Bologna
Michele Favalli , University of Bologna
pp. 524

DfT & On-line Test of High-Performance Data Converters: A Practical Case (Abstract)

José L. Huertas , Universidad de Sevilla
Juan A. Prieto , Universidad de Sevilla
Eduardo Peralías , Universidad de Sevilla
Adoración Rueda , Universidad de Sevilla
pp. 534
SESSION 22: MEMS FAULT MODELING AND DIAGNOSIS

Failure Mechanisms and Fault Classes for CMOS-Compatible Microelectromechanical Systems (Abstract)

S. Mir , TIMA Laboratory
D. Veychard , TIMA Laboratory
B. Courtois , TIMA Laboratory
A. Castillejo , TIMA Laboratory
J.M. Karam , TIMA Laboratory
pp. 541

Failure Modes for Stiction in Surface-Micromachined MEMS (Abstract)

Abhijeet Kolpekwar , Carnegie Mellon University
David Woodilla , Analog Devices
R.D.(Shawn) Blanton , Carnegie Mellon University
pp. 551

MEMS Fault Model Generation using CARAMEL (Abstract)

Abhijeet Kolpekwar , Carnegie Mellon University
Chris Kellen , Carnegie Mellon University
R. D.(Shawn) Blanton , Carnegie Mellon University
pp. 557
SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES

MAXIMIZATION OF POWER DISSIPATION UNDER RANDOM EXCITATION FOR BURN-IN TESTING (Abstract)

Jwu E Chen , Chung Hwa University
Chung Len Lee , National Chiao Tung University
Kuo Chan Huang , National Chiao Tung University
pp. 567

High-Coverage ATPG for Datapath Circuits with Unimplemented Blocks (Abstract)

Hyungwon Kim , University of Michigan
John P. Hayes , University of Michigan
pp. 577

Implicit Test Generation for Behavioral VHDL Models (Abstract)

Franco Fummi , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
Fabrizio Ferrandi , Politecnico di Milano
pp. 587
SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE

LEVERAGING NEW STANDARDS IN ATE SOFTWARE (Abstract)

John Oonk , Credence Systems Corp.
pp. 606

Testing The Design: The Evolution of Test Simulation (Abstract)

Tom Austin , Teradyne Incorporated
Craig Force , Texas Instruments
pp. 612
SESSION 25: PRACTICAL ATPG

ATPG in Practical and non-Traditional Applications (Abstract)

Brion Keller , IBM Corporation
Kevin McCauley , IBM Corporation
James Youngs , IBM Corporation
Joseph Swenton , IBM Corporation
pp. 632

Test Generation in VLSI Circuits for Crosstalk Noise (Abstract)

Melvin A. Breuer , University of Southern California
Weiyu Chen , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 641
SESSION 26: DFT THEORY

A Comprehensive Approach to the Partial Scan Problem using Implicit State Enumeration (Abstract)

Priyank Kalla , University of Massachusetts at Amherst
Maciej J. Ciesielski , University of Massachusetts at Amherst
pp. 651

A Novel Combinational Testability Analysis by Considering Signal Correlation (Abstract)

Shih-Chieh Chang , National Chung Cheng University
Chien-Chung Tsai , Mentor Graphics Corp.
Wen-Ben Jone , National Chung Cheng University
Shi-Sen Chang , National Chung Cheng University
pp. 658

DFT GUIDANCE THROUGH RTL TEST JUSTIFICATION AND PROPAGATION ANALYSIS (Abstract)

Alex Orailaglu , University of California at San Diego
Yiorgos Makris , University of California at San Diego
pp. 668
SESSION 27: MIXED-SIGNAL DFT
SESSION 29: MICROPROCESSOR TEST TOOLS

FakeFault: A Silicon Debug Software Tool for Microprocessor Embedded Memory Arrays (Abstract)

Ben Mathew , Silicon Graphics, Inc.
Young-Jun Kwon , Silicon Graphics, Inc.
Hong Hao , Silicon Graphics, Inc.
pp. 727
SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS

DIAGNOSIS AND CHARACTERIZATION OF TIMING-RELATED DEFECTS BY TIME-DEPENDENT LIGHT EMISSION (Abstract)

Phil Nigh , IBM Microelectronics
Pia Sanda , IBM T.J. Watson Research
Leendert Huisman , IBM Microelectronics
Dan Knebel , IBM T.J. Watson Research
J. C. Tsang , IBM T.J. Watson Research
Franco Motika , Micrus Corporation
J. A. Kash , IBM T.J. Watson Research
Moyra MC Manus , IBM T.J. Watson Research
Dave Vallett , IBM Microelectronics
pp. 733

NOVEL OPTICAL PROBING TECHNIQUE FOR FLIP CHIP PACKAGED MICROPROCESSORS (Abstract)

V.R.M. Rao , Intel Corporation
Mario Paniccia , Intel Corporation
Wai Mun Yee , Intel Corporation
Travis Eiles , Intel Corporation
pp. 740

On Applying Non-Classical Defect Models to Automated Diagnosis (Abstract)

Tracy Larrabee , University of California at Santa Cruz
Brian Chess , Hewlett-Packard Corp.
David B. Lavo , University of California at Santa Cruz
Hari Balachandran , Texas Instruments Inc.
F. Joel Ferguson , University of California at Santa Cruz
Jayashree Saxena , Texas Instruments Inc.
Kenneth M. Butler , Texas Instruments Inc.
pp. 748

A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures (Abstract)

Sandeep K. Gupta , University of Southern California
Yuan-Chieh Hsu , University of Southern California
pp. 758
SESSION 31: SYSTEM LEVEL TEST TECHNIQUES AND PROCESSES

A Fault Injection Environment for Microprocessor-based Boards (Abstract)

A. Benso , Politecnico di Torino
P. Prinetto , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
pp. 768

Boundary Scan BIST Methodology for Reconfigurable Systems (Abstract)

Yue-Tsang Chen , National Central University
Shung-Won Jeng , National Central University
Chauchin Su , National Central University
pp. 774

CAN MODEL-BASED AND CASE-BASED EXPERT SYSTEMS OPERATE TOGETHER? (Abstract)

Israel Beniaminy , IET Intelligent Electronics
David Joseph , IET Intelligent Electronics
Moshe Ben-Bassat , IET Intelligent Electronics
pp. 793
SESSION 32: THE NEED FOR SPEED mdash; TIMING AND JITTER TESTING

Measuring Jitter of High Speed Data Channels Using Undersampling Techniques (Abstract)

Wajih Dalal , Schlumberger Automated Test Equipment
Daniel Rosenthal , Schlumberger Automated Test Equipment
pp. 814
SESSION 33: VECTORS, INTERFACE, PROBES; ATE ISSUES IN AT-SPEED TEST

Alternative Interface Methods for Testing High Speed Bidirectional Signals (Abstract)

Q. Zhou , Georgia Institute of Technology
D. C. Keezer , Georgia Institute of Technology
pp. 824

P4 PROBE CARD- A SOLUTION FOR AT-SPEED, HIGH DENSITY, WAFER PROBING (Abstract)

Dan Higgins , Cerprobe Corporation
Rajiv Pandey , Cerprobe Corporation
pp. 836

CONTACTLESS GIGAHERTZ TESTING (Abstract)

V. Wittpahl , Gerhard-Mercator-Universit?t Duisburg
W. Mertin , Gerhard-Mercator-Universit?t Duisburg
A. Leyk , Gerhard-Mercator-Universit?t Duisburg
U. Behnke , Gerhard-Mercator-Universit?t Duisburg
pp. 843
SESSION 34: MANUFACTURING PROCESS MONITORING

A Highly Testable and Diagnosable Fabrication Process Test Chip (Abstract)

Ugonna Echeruo , Compaq Computer Corporation
William J. Bowhill , Compaq Computer Corporation
Dilip K. Bhavsar , Compaq Computer Corporation
David R. Akeson , Compaq Computer Corporation
pp. 853

CACHE RAM INDUCTIVE FAULT ANALYSIS WITH FAB DEFECT MODELING (Abstract)

T. M. Mak , Intel Corporation
Nermine Ramadan , Intel Corporation
Bob Roeder , Intel Corporation
Debika Bhattacharya , Intel Corporation
Jianlin Yu , University of California at Santa Cruz
Cheryl Prunty , Intel Corporation
Joel Ferguson , University of California at Santa Cruz
pp. 862

Semiconductor Manufacturing Process Monitoring using Built-In Self-Test for Embedded Memories (Abstract)

Dharmajaya Lukita , Delft University of Technology
Ivo Schanstra , Philips Semiconductors
Kees Veelenturf , Philips Semiconductors
Ad J. van de Goor , Delft University of Technology
Paul J. van Wijnen , Philips Semiconductors
pp. 872
SESSION 35: FAULT DETECTION AND IDDQ

DETECTING RESISTIVE SHORTS FOR CMOS DOMINO CIRCUITS (Abstract)

Edward J. McCluskey , Stanford University
Jonathan T.-Y. Chang , Stanford University
pp. 890

DEFECT LEVEL PREDICTION FOR I<sub>DDQ</sub> TESTING (Abstract)

Isao Kubota , Semiconductor Company, Sony Corp.
Yukio Okuda , Semiconductor Company, Sony Corp.
Masahiro Watanabe , Semiconductor Company, Sony Corp.
pp. 900
SESSION 36: ON-LINE TESTING

R-CBIST: An Effective RAM-based Input Vector Monitoring Concurrent BIST Technique (Abstract)

C. Halatsis , University of Athens
A. Paschalis , NCSR "Demokritos"
D. Nikolos , University of Patra
I. Voyiatzis , NCSR "Demokritos"
pp. 918
SESSION 37: CREATING EFFECTIVE TEST SEQUENCES

Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits (Abstract)

Janak H. Patel , University of Illinois at Urbana-Champaign
Ilker Hamzaoglu , University of Illinois at Urbana-Champaign
pp. 944
SESSION 38: TEST STANDARDS mdash; STILL EVOLVING

Standard Test Interface Language (STIL), Extending the Standard (Abstract)

Tony Taylor , Test Systems Strategies Incorporated
pp. 962

DEFINING ATPG RULES CHECKING IN STIL (Abstract)

Peter Wohl , Synopsys Inc.
John Waicukauski , Synopsys Inc.
pp. 971
SESSION 39: DESIGN VALIDATION AND DIAGNOSIS
SESSION 40: ALTERNATIVES TO IDDQ

Diagnosis method based on D Iddq probabilistic signatures: Experimental results (Abstract)

L. Boisvert , CAE ELECTRONIQUE LTEE
C. Thibeault , ?cole de Technologie Sup?rieure Montr?al
pp. 1019

PROCESS-TOLERANT TEST WITH ENERGY CONSUMPTION RATIO (Abstract)

Dechang Sun , University of Minnesota
Bapiraju Vinnakota , University of Minnesota
Wanli Jiang , University of Minnesota
pp. 1027

Detection Of Bridging Faults In Logic Resources of Configurable FPGAs Using I<sub>DDQ</sub> (Abstract)

F. Lombardi , Texas A&M University
L. Zhao , Lucent Technologies
D. M. H. Walker , Texas A&M University
pp. 1037
SESSION 41: BIST GENERATOR AND ARCHITECTURES

Automated Synthesis of Large Phase Shifters for Built-In Self-Test (Abstract)

Jerzy Tyszer , Poznan University of Technology
Nagesh Tamarapalli , Mentor Graphics Corporation
Janusz Rajski , Mentor Graphics Corporation
pp. 1047

Deterministic BIST with Multiple Scan Chains (Abstract)

Gundolf Kiefer , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
pp. 1057

An Almost Full-Scan BIST Solution — Higher Fault Coverage and Shorter Test Application Time (Abstract)

Sudipta Bhawmik , Bell Laboratories, Lucent Technologies
Huan-Chih Tsai , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 1065
SESSION 42: NEW IDEAS IN LOGIC DIAGNOSIS

Probabilistic Mixed-Model Fault Diagnosis (Abstract)

Ismed Hartanto , Hewlett-Packard Company
Brian Chess , University of California at Santa Cruz
David B. Lavo , University of California at Santa Cruz
Tracy Larrabee , University of California at Santa Cruz
pp. 1084

MODELING THE UNKNOWN! TOWARDS MODEL-INDEPENDENT FAULT AND ERROR DIAGNOSIS (Abstract)

Vamsi Boppana , Fujitsu Laboratories of America, Inc.
Masahiro Fujita , Fujitsu Laboratories of America, Inc.
pp. 1094
SESSION 43: EMBEDDED MEMORIES

SRAM-Based FPGA?s: Testing the LUT/RAM Modules (Abstract)

M. Renovell , LIRMM-UM2
J. M. Portal , LIRMM-UM2
Y. Zorian , Logic Vision Inc.
J. Figueras , UPC Diagonal
pp. 1102

BUILT IN SELF REPAIR FOR EMBEDDED HIGH DENSITY SRAM (Abstract)

Hai Pham , Bell Laboratories - Lucent Technologies
Yervant Zorian , Bell Laboratories - Lucent Technologies
Ilyoung Kim , Bell Laboratories - Lucent Technologies
Goh Komoriya , Bell Laboratories - Lucent Technologies
Frank P. Higgins , Bell Laboratories - Lucent Technologies
Jim L. Lewandowski , Bell Laboratories - Lucent Technologies
pp. 1112

How We Test Siemens? Embedded DRAM Cores (Abstract)

Roderick McConnell , Siemens Semiconductor
Detlev Richter , Siemens Semiconductor
Udo Möller , Siemens Semiconductor
pp. 1120
PANEL 1: GOOD ENOUGH QUALITY mdash; WHEN IS ?ENOUGH? ENOUGH?

"Enough Is Enough Already..." (PDF)

William R. Simpson , Institute for Defense Analyses
pp. 1127

Test: When Is "Enough" Enough? (PDF)

Bret A. Stewart , Texas Instruments
pp. 1128

How Much Testing Is Enough...? (PDF)

Susana Stoica , Ford Motor Company
pp. 1129
PANEL 2: TWO WORLDS COLLIDE: MIXED SIGNAL ASIC TESTING

Testing Mixed Signal SOCs (PDF)

Mark Burns , Texas Instruments, Inc.
pp. 1132

When Two Worlds Merge (PDF)

Ken Lanier , LTX Corporation
pp. 1133
PANEL 3: DIAGNOSTIC WAR STORIES: WHAT SAVED THE DAY? A TECHNIQUE DEBATE
PANEL 4: SCALING DEEPER TO SUBMICRON: ON-LINE TESTING TO THE RESCUE
PANEL 5: THE ROAD TO SYSTEM-ON-CHIP TEST mdash; IT?S A MATTER OF CORES mdash; IS IT?

Learning to Knit SOCs Profitably (PDF)

Todd Rockoff , SIMD Solutions, Inc
pp. 1142
PANEL 6: BIST VS. ATE: WHICH IS BETTER, FOR WHICH IC TESTS?

BIST: Required for Embedded DRAM (PDF)

Satoru Tanoi , OKI Electric Industry Co., Ltd.
pp. 1149
PANEL 7: HOW REAL IS THE NEW 1997 SIA ROADMAP?

Just How Real Is the SIA Roadmap? (PDF)

WAYNE NEEDHAM , INTEL CORPORATION
pp. 1151

The Rise and Fall of the ATE Industry (PDF)

Todd Rockoff , SIMD Solutions, Inc
pp. 1154

Functional ATE CAN Meet the Challenges (PDF)

Burnell G. West , Schlumberger Technologies
pp. 1155
PANEL 8: ACADEMIC RESEARCH: POWER PLANT OR IVORY TOWER?
PANEL 9: FLYING PROBERS mdash; A NEW ERA IN LOADED BOARD FIXTURELESS TEST
PANEL 10: STUCK-AT FAULT: THE FAULT MODEL OF CHOICE FOR THE THIRD MILLENNIUM!?

Stuck-At Fault: A Fault Model for the Next Millennium (PDF)

Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 1166

Buying Time for the Stuck-At Fault Model (PDF)

Jeff Rearick , Hewlett-Packard Company
pp. 1167
BEST PAPER:

Current Signatures: Application (Abstract)

Anne E. Gattiker , Carnegie Mellon University
Wojciech Maly , Carnegie Mellon University
pp. 1168
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