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Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) (1998)
Washington, D.C. USA
Oct. 18, 1998 to Oct. 23, 1998
ISSN: 1089-3539
ISBN: 0-7803-5093-6
pp: 641
Weiyu Chen , University of Southern California
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects.
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer, "Test Generation in VLSI Circuits for Crosstalk Noise", Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), vol. 00, no. , pp. 641, 1998, doi:10.1109/TEST.1998.743208
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