The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (1997)
Washington D.C.
Nov. 1, 1997 to Nov. 6, 1997
ISSN: 1089-3539
ISBN: 0-7803-4210-0
TABLE OF CONTENTS
INTRODUCTORY SECTION

Reviewers (PDF)

pp. 14

Author Index (PDF)

pp. 1053
SESSION 1: PLENARY
SESSION 2: DYNAMIC CURRENT TESTING

Transient Power Supply Voltage (V <sub>DDT</sub> ) Analysis for Detecting IC Defects (Abstract)

Edward I. Cole Jr. , Sandia National Laboratories
Jerry M. Soden , Sandia National Laboratories
Christopher L. Henderson , Sandia National Laboratories
Charles F. Hawkins , University of New Mexico
Patrick L. Candelaria , Sandia National Laboratories
Richard W. Beegle , Sandia National Laboratories
Paiboon Tangyunyong , Sandia National Laboratories
Daniel L. Barton , Sandia National Laboratories
pp. 23

I<sub>DD</sub> Pulse Response Testing Applied to Complex CMOS ICs (Abstract)

S. Pour-Mozafari , New Mexico State University
J. S. Beasley , New Mexico State University
C. J. Apodaca , Intel Corporation
D. Huggett , New Mexico State University
A. W. Righter , Sandia National Laboratories
pp. 32
SESSION 3: EMBEDDED CORE TESTING

Modifying User-Defined Logic for Test Access to Embedded Cores (Abstract)

Nur A. Touba , University of Texas at Austin
Bahram Pouya , University of Texas at Austin
pp. 60
SESSION 4: ATE HARDWARE IMPROVEMENTS FOR HIGH-SPEED TEST

An Efficient Method for Compressing Test Data (Abstract)

Dong Sam Ha , Virginia Polytechnic Institute and State University
Takahiro Yamaguchi , Advantest Laboratories Ltd.
Marco Tilgner , Tokyo Institute of Technology
Masahiro Ishida , Advantest Laboratories Ltd.
pp. 79

Hardware Compression Speeds on Bitmap Fail Display (Abstract)

John Donaldson , Teradyne, Inc.
Bob Gage , Teradyne, Inc.
Ben Brown , Teradyne, Inc.
Alexander Joffe , Teradyne, Inc.
pp. 89

Low-Cost ATE Pin Electronics for Multigigibit-per-Second at-Speed Test (Abstract)

R. J. Wenzel , Georgia Institute of Technology
D. C. Keezer , Georgia Institute of Technology
pp. 94
SESSION 5: MCM SYSTEMS TEST

A Simulation-Based JTAG ATPG Optimized for MCMs (Abstract)

Andrew Flint , AT&T Wireless Services
pp. 101

Testing The 400-MHz IBM Generation-4 CMOS Chip (Abstract)

Dale E. Hoffman , International Business Machines Corporation
Mary P. Kusko , IBM Microelectronics
William V. Huott , International Business Machines Corporation
Bryan J. Robbins , International Business Machines Corporation
Timothy J. Koprowski , International Business Machines Corporation
Thomas G. Foote , International Business Machines Corporation
pp. 106

Testing the Enterprise IBM System/390™ Multi Processor (Abstract)

Kevin Melocco , IBM Microelectronics
Ulrich Baur , IBM Development Lab Germany
Georg Goecke , IBM Development Lab Germany
Otto A. Torreiter , IBM Development Lab Germany
pp. 115
SESSION 6: UNPOWERED OPENS LECTURE SERIES

Capacitive Leadframe Testing (PDF)

Ted T. Turner , Hewlett-Packard Company
pp. 124
SESSION 7: IDDQ TESTING

Experiences with Implementation of I<sub>DDQ</sub> Test for Identification and Automotive Products (Abstract)

Ralf Arnold , Philips Semiconductors
Horst-Udo Wedekind , Philips Semiconductors
Thorsten Bode , Philips Semiconductors
Markus Feuser , Philips Semiconductors
pp. 127

I<sub>DDQ</sub> Characterization in Submicron CMOS (Abstract)

Joan Figueras , Universitat Politècnica de Catalunya
Antoni Ferré , Universitat Politècnica de Catalunya
pp. 136

Intrinsic Leakage in Low Power Deep Submicron CMOS ICs (Abstract)

Charles F. Hawkins , University of New Mexico
Ali Keshavarzi , Intel Corporation
Kaushik Roy , Purdue University
pp. 146

Current Signatures: Application (Abstract)

Wojciech Maly , Carnegie Mellon University
Anne E. Gattiker , Carnegie Mellon University
pp. 156
SESSION 8: PROGRESS ON STANDARDS AND BENCHMARKS

1149.5: Now It?s a Standard, So What? (Abstract)

Harry Hulvershorn , LogicVision Canada Inc.
pp. 166

IEEE P1149.4 - ALMOST A STANDARD (Abstract)

Adam Cron , Motorola
pp. 174

Analog and Mixed-Signal Benchmark Circuits - First Release (Abstract)

K. Arabi , Opmaxx, Inc.
A. Rueda , CNM, Seville
P. Goteti , University of Washington
B. Kaminska , Opmaxx, Inc.
J. L. Huertas , CNM, Seville
M. Soma , University of Washington
B. Kim , Tufts University
I. Bell , University of Hull
pp. 183
SESSION 9: MEMORY TEST

A 256Meg SDRAM BIST for Disturb Test Application (Abstract)

Dan Cline , Texas Instruments, Inc.
Theo J. Powell , Texas Instruments, Inc.
Francis Hii , Texas Instruments Singapore, PTE. LTD.
pp. 200

A SELF-TEST CIRCUIT FOR EVALUATING MEMORY SENSE-AMPLIFIER SIGNAL (Abstract)

R. Dean Adams , Dartmouth College
Patrick R. Hansen , Dartmouth College
Edmond S. Cooley , Dartmouth College
pp. 217
SESSION 10: TEST SYNTHESIS

Testability Enhancement for Behavioral Descriptions Containing Conditional Statements (Abstract)

Kelly A. Ockunzzi , Case Western Reserve University
Christos A. Papachristou , Case Western Reserve University
pp. 236
SESSION 11: UNPOWERED OPENS LECTURE SERIES

Unpowered Opens Test with X-Ray Laminography (PDF)

Stig Oresjo , Hewlett-Packard Company
pp. 276
SESSION 12: MICROPROCESSOR TEST I

MANUFACTURING PATTERN DEVELOPMENT FOR THE ALPHA 21164 MICROPROCESSOR (Abstract)

Carol Stolicny , Digital Semiconductor
Richard Davies , Digital Semiconductor
Pamela McKernan , Digital Semiconductor
Tuyen Truong , Digital Semiconductor
pp. 278

DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500 (Abstract)

Jay Fleischman , Hewlett Packard
Jeff Brauch , Hewlett Packard
pp. 286

PENTIUM? PRO PROCESSOR DESIGN FOR TEST AND DEBUG (Abstract)

Derek Feltham , Intel Corporation
Adrian Carbine , Intel Corporation
pp. 294
SESSION 13: DIAGNOSIS & FAILURE ANALYSIS LECTURE SERIES

Signature Analysis for IC Diagnosis and Failure Analysis (Abstract)

Christopher L. Henderson , Sandia National Laboratories
Jerry M. Soden , Sandia National Laboratories
pp. 310

APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWARE (Abstract)

Franco Motika , Micrus Corporation
Donato Forlenza , Micrus Corporation
Phil Nigh , IBM Microelectronics
pp. 319
SESSION 14: DETERMINISTIC BIST

Test Width Compression for Built-In Self Testing (Abstract)

Brian T. Murray , General Motors R&D Center
Jian Liu , Boston University
Minyao Zhu , Boston University
Krishnendu Chakrabarty , Boston University
pp. 328

On Using Machine Learning for Logic BIST (Abstract)

Christophe FAGOT , UNIVERSITE MONTPELLIER II
Christian LANDRAULT , UNIVERSITE MONTPELLIER II
Patrick GIRARD , UNIVERSITE MONTPELLIER II
pp. 338

Using BIST Control for Pattern Generation (Abstract)

Hans-Joachim Wunderlich , University of Stuttgart,
Gundolf Kiefer , University of Stuttgart
pp. 347
SESSION 15: COMPONENTS FOR MCMS: KNOWN-GOOD-DIE AND SUBSTRATES

ASIC Manufacturing Test Cost Prediction at Early Design Stage (Abstract)

Tom Chen , Colorado State University
Von-Kyoung Kim , Sun Microelectronics
Mick Tegethoff , Celestica Inc.
pp. 356

Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study (Abstract)

C. M. Krishna , University of Massachusetts at Amherst
Phil Nigh , IBM
Adit D. Singh , Auburn University
pp. 362

A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates (Abstract)

K. E. Newman , Georgia Institute of Technology
D. C. Keezer , Georgia Institute of Technology
pp. 370
SESSION 16: MIXED-SIGNAL SEMINAR: MEASUREMENT TECHNIQUES

DYNAMIC TESTING OF ADCS USING WAVELET TRANSFORMS (Abstract)

Takahiro Yamaguchi , ADVANTEST Laboratories, Ltd.
Mani Soma , University of Washington
pp. 379
SESSION 17: MICROPROCESSOR TEST II

Testability Features of AMD-K6™ Microprocessor (Abstract)

Imtiaz P. Shaik , Advanced Micro Devices
Siyad C. Ma , Advanced Micro Devices
R. Scott Fetherston , Advanced Micro Devices
pp. 406

Next Generation PowerPC™ Microprocessor Test Strategy Improvements (Abstract)

Carol Pyron , Motorola, Inc.
James Golab , Motorola, Inc.
Javier Prado , Motorola, Inc.
pp. 414

A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors (Abstract)

Grady Giles , Motorola, Inc.
Alfred L. Crouch , Motorola, Inc.
Renny Eisele , Motorola, Inc.
Michael Mateja , Motorola, Inc.
Dale Amason , Motorola, Inc.
pp. 424
SESSION 18: DIAGNOSIS AND FAILURE ANALYSIS LECTURE SERIES PANEL

IC Diagnosis: Industry Issues (PDF)

Christopher L. Henderson , Sandia National Laboratories
Jerry M. Soden , Sandia National Laboratories
pp. 435
SESSION 19: DESIGN FOR DELAY TEST

Design for Primitive Delay Fault Testability (Abstract)

Angela Krstić , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 436

Scan Latch Design for Delay Test (Abstract)

Jacob Savir , New Jersey Institute of Technology
pp. 446

Delay Testing with Clock Control: An Alternative to Enhanced Scan (Abstract)

Ramesh C. Tekumalla , University of Massachusetts at Amherst
Prem R. Menon , University of Massachusetts at Amherst
pp. 454
SESSION 20: CONCURRENT CHECKING

AN ON-LINE SELF-TESTING SWITCHED-CURRENT INTEGRATOR (Abstract)

Ian M. Bell , University of Hull
Osama K. Abu-Shahla , University of Hull
pp. 463

ON-LINE TESTABLE LOGIC DESIGN FOR FPGA IMPLEMENTATION (Abstract)

A. L. Burress , North Carolina A&T State University
P. K. Lala , North Carolina A&T State University
pp. 471

A Parameterized VHDL Library for On-Line Testing (Abstract)

S. Roy , Lucent Technologies
C. Stroud , University of Kentucky
M. Ding , University of Kentucky
S. Seshadri , University of Kentucky
R. Karri , Lucent Technologies
S. Wu , Lucent Technologies
I. Kim , Lucent Technologies
pp. 479
SESSION 21: MIXED-SIGNAL SEMINAR: MEASUREMENTS USING P1149.4

Design, Fabrication and Use of Mixed-Signal IC Testability Structures (Abstract)

John E. McDermid , Hewlett Packard Company
Kozo Nuriya , Matsushita Electric Industrial Co., Ltd.
Katsuhiro Hirayama , Matsushita Electric Industrial Co., Ltd.
Kenneth P. Parker , Hewlett Packard Company
Rodney A. Browen , Hewlett Packard Company
Akira Matsuzawa , Matsushita Electric Industrial Co., Ltd.
pp. 489

desire to reduce (or eliminate) complex and in P1149.4 Environment (Abstract)

Chauchin Su , National Central University
Yue-Tsang Chen , National Central University
Shyh-Jye Jou , National Central University
pp. 499

IMPLEMENTATION OF MIXED CURRENT/VOLTAGE TESTING USING THE IEEE P1149.4 INFRASTRUCTURE (Abstract)

José Machado da Silva , Universidade do Porto
Ana C. Leão , Universidade do Porto
José C. Alves , Universidade do Porto
José Silva Matos , Universidade do Porto
pp. 509
SESSION 22: HIGH-PERFORMANCE PROBES AND SOCKETS
SESSION 23: BIST AND DFT ECONOMICS

BIST-Based Diagnostics of FPGA Logic Blocks (Abstract)

Charles Stroud , University of Kentucky
Miron Abramovici , Bell Labs - Lucent Technologies
Eric Lee , University of Kentucky
pp. 539

Scan Encoded Test Pattern Generation for BIST (Abstract)

Kun-Han Tsai , University of California at Santa Barbara
Janusz Rajski , Mentor Graphics Corporation
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 548

TO DFT OR NOT TO DFT? (Abstract)

R. D. Blanton , Carnegie Mellon University
A. Gattiker , Carnegie Mellon University
S. Wei , Carnegie Mellon University
P. K. Nag , Carnegie Mellon University
W. Maly , Carnegie Mellon University
pp. 557
SESSION 24: ON-LINE TESTING TECHNIQUES FOR VLSI

THE FAIL-STOP CONTROLLER AE11 (Abstract)

Th. Lindenkreuz , Robert Bosch GmbH
R. Stephan , Robert Bosch GmbH
E. Böhl , Robert Bosch GmbH
pp. 567

On-Line Testing Scheme for Clock?s Faults (Abstract)

Michele Favalli , University of Bologna
Bruno Riccó , University of Bologna
Cecilia Metra , University of Bologna
pp. 587
SESSION 25: DEFECT BEHAVIOR, TEST EFFICIENCY AND FAULT MODEL EXTENSION

Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits (Abstract)

F. Joel Ferguson , University of California at Santa Cruz
Haluk Konuk , Hewlett-Packard Company
pp. 597

Test Strategy Sensitivity to Defect Parameters (Abstract)

M. Renovell , Universit? de Montpellier II
Y. Bertrand , Universit? de Montpellier II
pp. 607

FAULT MODEL EXTENSION FOR DIAGNOSING CUSTOM CELL FAILS (Abstract)

Gilbert Vandling , International Business Machines Corp.
Thomas Bartenstein , International Business Machines Corp.
pp. 617
SESSION 26: MIXED-SIGNAL SEMINAR PANEL: ON-CHIP 1149.4, WHAT FOR?
SESSION 27: BOARD-LEVEL TEST METHODS

Optical Communication Channel Test Using BIST Approaches (Abstract)

Mathieu GAGNON , ?cole Polytechnique de Montr?al
Bozena KAMINSKA , Opmaxx, Inc.
pp. 626

Analog Fault Diagnosis for Unpowered Circuit Boards (Abstract)

Jiun-Lang Huang , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 640
SESSION 28: SOFTWARE FOR NEW TEST STRATEGIES

Pin Margin Analysis (Abstract)

Robert E. Huston , Credence Systems Corporation
pp. 655
SESSION 29: DESIGN-FOR-TEST TOPICS

Incorporating Physical Design-For-Test Into Routing (Abstract)

F. Joel Ferguson , University of California at Santa Cruz
Richard McGowen , Intel Corporation
pp. 685

Parameterizable Testing Scheme for FIR Filters (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Nilanjan Mukherjee , Lucent Technologies
Jerzy Tyszer , Poznali University of Technology
pp. 694

An Efficient Scheme to Diagnose Scan Chains (Abstract)

Ashutosh Das , Sun Microsystems Inc.
Sridhar Narayanan , Sun Microsystems Inc.
pp. 704

SCAN SYNTHESIS FOR ONE-HOT SIGNALS (Abstract)

Edward J. McCluskey , Stanford University
LaNae J. Avra , Stanford University
Subhasish Mitra , Stanford University
pp. 714
SESSION 30: SEQUENTIAL ATPG

Putting the Squeeze on Test Sequences (Abstract)

Elizabeth M. Rudnick , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 723

Sequential Test Generation with Advanced Illegal State Search (Abstract)

A. J. van de Goor , Delft University of Technology
J.Th. van der Linden , Delft University of Technology
M. H. Konijnenburg , Delft University of Technology
pp. 733

A Novel Functional Test Generation Method for Processors using Commercial ATPG (Abstract)

Raghuram S. Tupuri , Advanced Micro devices
Jacob A. Abraham , University of Texas at Austin
pp. 743

Testability analysis and ATPG on behavioral RT-level VHDL (Abstract)

Paolo PRINETTO , Politecnico di Torino
Fulvio CORNO , Politecnico di Torino
Matteo SONZA REORDA , Politecnico di Torino
pp. 753
SESSION 31: MIXED-SIGNAL SEMINAR: BIST/DFT

HABIST: Histogram-based Analog Built In Self Test (Abstract)

A. Frisch , Tektronix, Inc.
T. Almy , Tektronix, Inc.
pp. 760

EXPERIMENTAL RESULTS FOR CURRENT-BASED ANALOG SCAN (Abstract)

Tuyen D. Vu , Boeing Defense and Space Group
Mani Soma , University of Washington
Jason D. Moffatt , Boeing Defense and Space Group
Thomas M. Bocek , Boeing Defense and Space Group
pp. 768
SESSION 32: TEST ENGINEERING TOPICS

Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs (Abstract)

Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
Weiyu Chen , University of Southern California
pp. 809
SESSION 33: TOOLS AND TECHNIQUES FOR DEFECT TESTING

How Seriously Do You Take Possible-Detect Faults? (Abstract)

Robert Molyneaux , IBM Corporation
Rajesh Raina , Motorola Inc.
Charles Njinda , Chromatic Research, Inc.
pp. 819

ACT: A DFT Tool for Self-Timed Circuits (Abstract)

Ajay Khoche , Viewlogic Systems Inc.
Erik Brunvand , University of Utah
pp. 829

BART: A Bridging Fault Test Generator for Sequential Circuits (Abstract)

Janak H. Patel , University of Illinois at Urbana-Champaign
James P. Cusey , Dallas Semiconductor
pp. 838
SESSION 34: SPECIALIZED BIST GENERATORS

DS-LFSR: A New BIST TPG for Low Heat Dissipation (Abstract)

Sandeep K. Gupta , University of Southern California
Seongmoon Wang , University of Southern California
pp. 848

TREE-STRUCTURED LINEAR CELLULAR AUTOMATA AND THEIR APPLICATIONS AS PRPGS (Abstract)

X. Sun , University of Alberta Edmonton
K. Soon , University of Alberta Edmonton
J. Li , University of Alberta Edmonton
pp. 858

An Effective BIST Scheme for Arithmetic Logic Un i t s (Abstract)

Antonis Paschalis , NCSR "Demokritos"
Mihalis Psarakis , NCSR "Demokritos"
Dimitris Gizopoulos , NCSR "Demokritos"
Yervant Zorian , LogicVision, Inc .
pp. 868
SESSION 35: ADVANCES IN DIGITAL LOGIC DIAGNOSIS

Bridging Fault Diagnosis in the Absence of Physical Information (Abstract)

David B. Lavo , University of California at Santa Cruz
Jayashree Saxena , Texas Instruments Inc.
Kenneth M. Butler , Texas Instruments Inc.
Brian Chess , Hewlett-Packard Corp.
Tracy Larrabee , University of California at Santa Cruz
F. Joel Ferguson , University of California at Santa Cruz
pp. 887

FAULT DIAGNOSIS IN-SCAN-BASED BIST (Abstract)

Jerzy Tyszer , Poznań University of Technology
Janusz Rajski , Mentor Graphics Corporation
pp. 894
SESSION 36: MIXED-SIGNAL SEMINAR: FAULT MODELING

Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis (Abstract)

J. Hou , Georgia Institute of Technology
S. Chakrabarti , Georgia Institute of Technology
A. Chatterjee , Georgia Institute of Technology
A. Gomes , Georgia Institute of Technology
W. Kao , Cadence Design Systems
S. Cherubal , Georgia Institute of Technology
R. Voorakaranam , Georgia Institute of Technology
pp. 903

Fault Macromodeling for Analog/Mixed-Signal Circuits (Abstract)

Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
Chen-Yang Pan , University of California at Santa Barbara
pp. 913

Development of a MEMS Testing Methodology (Abstract)

R. D. (Shawn) Blanton , Carnegie Mellon University
Abhijeet Kolpekwar , Carnegie Mellon University
pp. 923
SESSION 37: NEW FRONTIERS IN TEST

Embedded At-Speed Test Probe (Abstract)

Mitch Aigner , Tektronix, Inc.
pp. 932

AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS (Abstract)

Yukiya Miura , Tokyo Metropolitan University
pp. 938

Supervisors for Testing Non-Deterministically Specified Systems (Abstract)

T. Savor , University of Waterloo
R. E. Seviora , University of Waterloo
pp. 948
SESSION 38: DESIGN VERIFICATION AND DIAGNOSIS

ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis (Abstract)

Kuang-Chien Chen , Fujitsu Labs. of America
Kwang-Ting Cheng , University of California at Santa Barbara
David Ihsin Cheng , Exemplar Logic Inc.
Shi-Yu Huang , National Semiconductor Corp.
pp. 974
SESSION 39: DELAY FAULT TESTING

Algorithms for Switch Level Delay Fault Simulation (Abstract)

Thomas G. Szymanski , Bell Labs, Lucent Technologies
Soumitra Bose , NEC USA
Vishwani D. Agrawal , Bell Labs, Lucent Technologies
pp. 982

Efficient Identification of Non-Robustly Untestable Path Delay Faults (Abstract)

Zhongcheng Li , University of California at Berkeley
Robert K. Brayton , University of California at Berkeley
Yinghua Min , Chinese Academy of Sciences
pp. 992

Effective Path Selection for Delay Fault Testing of Sequential Circuits (Abstract)

Tapan J. Chakraborty , Bell Labs, Lucent Technologies
Vishwani D. Agrawal , Bell Labs, Lucent Technologies
pp. 998
SESSION 40: TEST LANGUAGE STANDARDS

A UNIFIED INTERFACE FOR SCAN TEST GENERATION BASED ON STIL (Abstract)

Peter Wohl , Advanced Test Technologies Inc.
John Waicukauski , Advanced Test Technologies Inc.
pp. 1011
SESSION 41: ADVANCES IN PROBE TECHNOLOGY
PANEL 2: PARTIAL SCAN IS DEAD. LONG LIVE ALMOST-FULL SCAN!

The Case for Partial Scan (PDF)

Jeff Rearick , Hewlett-Packard Company
pp. 1032
PANEL 3: ETHICS, PROFESSIONALISM, AND ACCOUNTABILITY — DOES IT EXIST IN TEST?
PANEL 4: VISION SYSTEMS FOR BOARD TEST: MEETING THEIR PROMISE?
PANEL 6: SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT

SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT (PDF)

Phil Nigh , IBM
Rob Aitken , Hewlett-Packard
Peter Maxwell , Hewlett-Packard
Wojciech Maly , Carnegie Mellon University
Ken Butler , Texas Instruments
pp. 1037
PANEL 7: EMBEDDED CORE TEST PLUG-N-PLAY: IS IT ACHIEVABLE?

Thoughts on Core Integration and Test (PDF)

Thomas L. Anderson , Phoenix Technologies Ltd.
pp. 1039

Embedded Core Test Plug-n-Play: Is it Achievable? (PDF)

Rudy Garcia , Schlumberger Technologies,
pp. 1040
PANEL 8: ON-LINE TESTING, INDUSTRIAL PRACTICE AND PERSPECTIVES
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