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2013 IEEE International Test Conference (ITC) (1997)
Washington D.C.
Nov. 1, 1997 to Nov. 6, 1997
ISSN: 1089-3539
ISBN: 0-7803-4210-0
pp: 838
Janak H. Patel , University of Illinois at Urbana-Champaign
James P. Cusey , Dallas Semiconductor
ABSTRACT
The need for test generation tools which target bridging faults in addition to stuck-at faults is growing. This work introduces BART, a new bridging-fault-targeted test generator based upon HITEC and E-PROOFS, and gauges its performance against that of other techniques for bridging fault testing. A new circuit modification is proposed which allows a single bridging fault to be represented as a collection of four stuck-at faults. This modification is refined so that lines can be justified so as to maximize the probability that the voltage on one of the bridged nodes is corrupted enough to represent an incorrect logic value. This refinement uses the concept of "strong" and "weak" logic values, which gauge the resistance of the path between a gate output and the driving rail. BART was able to produce test sets which gave reasonable coverage for sequential circuits as well as combinational circuits.
INDEX TERMS
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CITATION
Janak H. Patel, James P. Cusey, "BART: A Bridging Fault Test Generator for Sequential Circuits", 2013 IEEE International Test Conference (ITC), vol. 00, no. , pp. 838, 1997, doi:10.1109/TEST.1997.639698
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