The Community for Technology Leaders
2013 IEEE International Test Conference (ITC) (1996)
Washington, D.C.
Oct. 20, 1996 to Oct. 25, 1996
ISSN: 1089-3539
ISBN: 0-7803-3543-0
TABLE OF CONTENTS
Introductory Section

Reviewers (PDF)

pp. 944

Author Index (PDF)

pp. 950
Session 1: Plenary

null (PDF)

pp. null
Keynote Address
Invited Address
Session 2.0: Automatic Test Generation

null (PDF)

pp. null

Test Generation For Ultra-Large Circuits Using ATPG Constraints And Test-Pattern Templates (Abstract)

John Waicukauski , Advanced Test Technologies Inc., Tualatin, OR
Peter Wohl , Advanced Test Technologies Inc., Williston, VT
pp. 13

Test Pattern Generation for Circuits with Asynchronous Signals based on Scan (Abstract)

Mitsuo Teramoto , NTT System Electronics Laboratories, Japan
Tomoo Fukazawa , NTT System Electronics Laboratories, Japan
pp. 21

Accelerated Compact Test Set Generation for Three-State Circuits (Abstract)

A. J. van de Goor , Delft University of Technology, The Netherlands
J. Th. van der Linden , Delft University of Technology, The Netherlands
M. H. Konijnenburg , Delft University of Technology, The Netherlands
pp. 29

Comparing topological, symbolic and GA-based ATPGs: an experimental approach (Abstract)

F. Corno , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
P. Prinetto , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
pp. 39
Session 3.0: BIST: Architectures And Generators

null (PDF)

pp. null

BIST Fault Diagnosis In Scan-Based VLSI Environments (Abstract)

Yuejian Wu , Northern Telecom, Ontario, Canada
Saman Adham , Northern Telecom, Ontario, Canada
pp. 48

LFSR Reseeding As A Component of Board Level BIST (Abstract)

Pieter M. Trouborst , Northern Telecom, Ontario, Canada
pp. 58

Using ILA Testing for BIST in FPGAs (Abstract)

Eric Lee , University of Kentucky, Lexington, KY
Charles Stroud , University of Kentucky, Lexington, KY
Srinivasa Konala , University of Kentucky, Lexington, KY
Miron Abramovici , Bell Labs - Lucent Technologies, Murray Hill, NJ
pp. 68

An Effective BIST Scheme for Datapaths (Abstract)

Dimitris Gizopoulos , II&T, NCSR "Demokritos", Athens, Greece
Yervant Zorian , Lucent Bell Laboratories, Princeton, NJ
Antonis Paschalis , II&T, NCSR "Demokritos", Athens, Greece
pp. 76
Session 4.0: New Test Considerations For Mixed-Signal Devices

null (PDF)

pp. null

Four Multi Probing Test For 16 Bit DAC With Vertical Contact Probe Card (Abstract)

Seiji Sasho , Asahi Kasei Microsystems Co., Japan
Teruhisa Sakata , Japan Electronic Materials Co., Japan
pp. 86

Testing The Digital Modulation of PHS Devices (Abstract)

Koji Asami , Advantest Corporation, Saitama, Japan
pp. 99
Session 5.0: Topics In Test Hardware

null (PDF)

pp. null

High-Speed I<sub>DDQ</sub> Measurement Circuit (Abstract)

Kenji Isawa , ADVANTEST Corporation, Japan
Yoshihiro Hashimoto , ADVANTEST Corporation, Japan
pp. 112

Extending Calibration Intervals (Abstract)

Solomon Max , LTX Corporation - Westwood, MA
pp. 118

Manufacturing Test of Fibre Channel Communications Cards And Optical Subassemblies (Abstract)

Steven DeFoster , IBM AS/400 Division, Rochester, MN
Kirk Kottschade , IBM AS/400 Division, Rochester, MN
Paul Sendelbach , IBM AS/400 Division, Rochester, MN
Dennis Karst , IBM AS/400 Division, Rochester, MN
Matthew Peterson , IBM AS/400 Division, Rochester, MN
pp. 127
Session 6.0: Practical And Higher-Level Fault Simulation

null (PDF)

pp. null

A Universal Technique for Accelerating Simulation of Scan Test Patterns (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR
Bejoy G. Oomman , Genesys Testware, Fremont, CA
John Waicukauski , Advanced Test Technologies, Tualatin, OR
pp. 135

On Potential Fault Detection in Sequential Circuits (Abstract)

Janak H. Patel , University of Illinois, Urbana
Irith Pomeranz , University of Iowa, Iowa City
pp. 142

Improving Gate Level Fault Coverage by RTL Fault Grading (Abstract)

Weiwei Mao , Lucent Technologies, Allentown, PA
Ravi K. Gulati , Texas Instruments, Inc., Dallas, TX
pp. 150

Distributed Mixed Level Logic And Fault Simulation On The Pentium?Pro Microprocessor (Abstract)

Jacob A. Abraham , University of Texas at Austin
Srinivasu Pappula , Intel Corporation
Sankaran Karthik , National Semiconductor India Pvt. Ltd.
Glidden Martin , Intel Corporation
Manuel d?Abreu , Level One Communications
Praveen Vishakantaiah , Intel Corporation
Bob Stettler , Intel Corporation
Mark Aitken , Intel Corporation
pp. 160
Session 7.0: BIST Pattern Generation

null (PDF)

pp. null

Altering A Pseudo-Random Bit Sequence For Scan-Based BIST (Abstract)

Nur A. Touba , University of Texas, Austin, TX
Edward J. McCluskey , Stanford University
pp. 167

MFBIST: A BIST Method For Random Pattern Resistant Circuits (Abstract)

Charles R. Kime , University of Wisconsin-Madison
Mohammed F. AlShaibi , Ministry of Interior, Saudi Arabia
pp. 176

Two-Dimensional Test Data Decompressor for Multiple Scan Designs (Abstract)

J. Rajski , Mentor Graphics Corporation, Wilsonville, OR, USA
J. Tyszer , The Franco-Polish School of New Information and Communication Tech., Poznan, Poland
N. Zacharia , McGill University, Montr?al, Canada
J. A. Waicukauski , Mentor Graphics Corporation, Wilsonville, OR, USA
pp. 186

Mixed-Mode BIST Using Embedded Processors (Abstract)

Sybille Hellebrand , University of Siegen, Germany
Andre Hertwig , University of Siegen, Germany
Hans-Joachim Wunderlich , University of Siegen, Germany
pp. 195
Session 8.0: Testing of Asynchronous Circuits

null (PDF)

pp. null

Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation (Abstract)

Marly Roncken , Philips Research Laboratories, the Netherlands
Eric Bruls , Philips Research Laboratories, the Netherlands
pp. 205

Optimal Scan for Pipelined Testing: An Asynchronous Foundation (Abstract)

Marly Roncken , Philips Research Laboratories, The Netherlands
Wim Verhaegh , Philips Research Laboratories, The Netherlands
Emile Aarts , Philips Research Laboratories, The Netherlands
pp. 215

An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention (Abstract)

Volker Sch?ber , Universit?t Hannover, Institut f?r Theoretische Elektrotechnik
Thomas Kiel , Universit?t Hannover, Institut f?r Theoretische Elektrotechnik
pp. 225

Synthesis-for-Initializability of Asynchronous Sequential Machines (Abstract)

Steven M. Nowick , Columbia University, New York
Montek Singh , Columbia University, New York
pp. 232
Session 9.0: Industry Impact: Screening, Test, And Measurement Breakthroughs

null (PDF)

pp. null

Burn-in Elimination of a High Volume Microprocessor Using I<sub>DDQ</sub> (Abstract)

Thomas Soo , Intel Technology Sdn. Bhd., Penang, Malaysia
Timothy R. Henry , Intel Corporation, Chandler, AZ
pp. 242

IDDQ And AC Scan: The War Against Unmodelled Defects (Abstract)

Kathleen R. Kollitz , Hewlett-Packard Company
Peter C. Maxwell , Hewlett-Packard Company
Robert C. Aitken , Hewlett-Packard Company
Allen C. Brown , Hewlett-Packard Company
pp. 250

High Resolution I<sub>DDQ</sub> Characterization and Testing - Practical Issues (Abstract)

Jerry M. Soden , Failure Analysis, Sandia National Laboratories
Alan W. Righter , MCM Applications, Sandia National Laboratories
Richard W. Beegle , CAE and Test, Sandia National Laboratories
pp. 259

Novel Optical Probing System With Submicron Spatial Resolution For Internal Diagnosis of VLSI Circuits (Abstract)

Y. Goto , Fujitsu Laboratories Ltd., Japan
Y. Umehara , Advantest Corporation, Japan
J. Matsumoto , Advantest Corporation, Japan
K. Ozaki , Fujitsu Laboratories Ltd., Japan
H. Sekiguchi , Fujitsu Laboratories Ltd., Japan
S. Wakana , Fujitsu Laboratories Ltd., Japan
pp. 269
Session 10.0: Fault Simulation And Diagnosis of Delay Faults

null (PDF)

pp. null

An Exact Non-Enumerative Fault Simulator For Path-Delay Faults (Abstract)

Michael L. Bushnell , Rutgers University, Piscataway, NJ
Vishwani D. Agrawal , Lucent Technologies, Murray Hill, NJ
Marwan A. Gharaybeh , Rutgers University, Piscataway, NJ
pp. 276

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms (Abstract)

S. Pravossoudovitch , Universite Montpellier II/CNRS, France
P. Girard , Universite Montpellier II/CNRS, France
B. Rodriguez , Universite Montpellier II/CNRS, France
C. Landrault , Universite Montpellier II/CNRS, France
pp. 286

Dignostic Fault Equivalence Identification Using Redundancy Information & Structural Analysis (Abstract)

Vamsi Boppana , University of Illinois
W. Kent Fuchs , Purdue University
Ismed Hartanto , University of Illinois
pp. 294
Session 11.0: Memory Test: Design For Testability

null (PDF)

pp. null

Self-Learning Signature Analysis for Non-Volatile Memory Testing (Abstract)

Marcello Dalpasso , Istituto di Ingegneria - Universit? di Ferrara, Italy
Piero Olivo , Istituto di Ingegneria - Universit? di Ferrara, Italy
pp. 303

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM (Abstract)

Fumihiro Okuda , LTEC Corporation
Shinji Komori , Advanced Technology R&D Center
Akihiko Yasuoka , ULSI Laboratory
Tetsuo Tada , System LSI Laboratory
Narumi Sakashita , Advanced Technology R&D Center
Mitsuhiro Hamada , ULSI Laboratory
Haruhiko Abe , Advanced Technology R&D Center
Ken'ichi Shimomura , Advanced Technology R&D Center
Hiroki Shimano , Advanced Technology R&D Center
Kazuo Kyuma , Advanced Technology R&D Center
pp. 319
Session 12.0: Board Test Challenges And Solutions

null (PDF)

pp. null

Analog/Digital Testing of Loaded Boards Without Dedicated Test Points (Abstract)

Louis Balme , TIMA Laboratory
Christophe Vaucher , True Test Techniques and Training
pp. 325

Opens Board Test Coverage: When Is 99% Really 40%? (Abstract)

Kenneth P. Parker , Manufacturing Test Division, Hewlett-Packard Company, Loveland, CO
Mick M. V. Tegethoff , Manufacturing Test Division, Hewlett-Packard Company, Loveland, CO
Ken Lee , HP Laboratories, Palo Alto, CA
pp. 333

A Roadmap for Boundary-Scan Test Reuse (Abstract)

Tom Conner , Teradyne, Inc.
Gene Wedge , Teradyne, Inc.
pp. 340
Session 13.0: Delay-Fault Testing I

null (PDF)

pp. null

Local Transformations and Robust Dependent Path Delay Faults (Abstract)

Bernd Becker , Albert-Ludwigs-University, Freiburg, Germany
Uwe Sparmann , University of Saarland, Saarbr?cken, Germany
Harry Hengster , Albert-Ludwigs-University, Freiburg, Germany
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 347

Detecting Delay Flaws by Very-Low-Voltage Testing (Abstract)

Jonathan T.-Y. Chang , Stanford University
Edward J. McCluskey , Stanford University
pp. 367
Session 14.0: Microprocessor Test

null (PDF)

pp. null

Testability Features for a Submicron Voice-coder ASIC (Abstract)

F. Pichon , Common Techniques and Technologies Unit
pp. 377

A BIST Methodology For Comprehensive Testing of RAM With Reduced Head Dissipation (Abstract)

Sandeep K. Gupta , Sandeep K. Gupta, Los Angeles, CA
Hugo Cheung , Rockwell Semiconductor Systems, Newport Beach, CA
pp. 386

DFT Strategy For Intel Microprocessors (Abstract)

Naga Gollakota , Intel Corporation, Chandler, AZ
pp. 396
Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard

null (PDF)

pp. null
Session 16.0: Delay Fault Testing II

null (PDF)

pp. null

Identification and Test Generation for Primitive Faults (Abstract)

Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Angela Krstic , University of California, Santa Barbara
Srimat T. Chakradhar , NEC USA, Princeton, NJ
pp. 423

Test Generation For Global Delay Faults (Abstract)

D. M. H. Walker , Texas A&M University, College Station, TX
G. M. Luong , Texas A&M University, College Station, TX
pp. 433

ATPD: An Automatic Test Pattern Generator For Path Delay Faults (Abstract)

S. Tragoudas , Southern Illinois University, Carbondale
D. Karayiannis , Southern Illinois University, Carbondale
pp. 443
Session 17.0: Software For New Test Strategies

null (PDF)

pp. null

Scan Design Oriented Test Technique For VLSI's Using ATE (Abstract)

Toshinobu Kanai , Advantest Corporation, Japan
Yasuji Oyama , Advantest Corporation, Japan
Hironobu Niijima , Advantest Corporation, Japan
pp. 453

Virtual Test of Noise And Jitter Parameters (Abstract)

G. Reinwardt , Advantest (Europe) GmbH, Germany
K. Helmreich , Advantest (Europe) GmbH, Germany
pp. 461

A Novel Approach to the Analysis of VLSI Device Test Programs (Abstract)

Wanchun Shi , Academia Sinica, China
Yuhai Ma , Tsinghua University, China
pp. 471
Session 18.0: Innovations In Current Testing

null (PDF)

pp. null

Digital Integrated Circuit Testing using Transient Signal Analysis (Abstract)

James F. Plusquellic , University of Pittsburgh
Donald M. Chiarulli , University of Pittsburgh
Steven P. Levitan , University of Pittsburgh
pp. 481

Towards an Effective I<sub>DDQ</sub> Test Vector Selection and Application Methodology (Abstract)

Urbain Swerts , Alcatel Telecom, Belgium
Marc Darquennes , Alcatel Telecom, Belgium
Jos van Sas , Alcatel Telecom, Belgium
pp. 491

Correlating Defects To Functional And I<sub>DDQ</sub> Tests (Abstract)

James R. Pair , Texas Instruments, Inc., Dallas, TX
Bernard G. Carbajal III , Texas Instruments, Inc., Dallas, TX
Theo J. Powell , Texas Instruments, Inc., Dallas, TX
pp. 501
Session 19.0: Mixed-Signal DFT And Fault Simulation

null (PDF)

pp. null

Defect-Oriented vs Schematic-Level Based Fault Simulation For Mixed-Signal ICs (Abstract)

Carles Ferrer , CNM(CSIC) - University Aut?noma de Barcelona, Spain
Jordi P?rez , CNM(CSIC) - University Aut?noma de Barcelona, Spain
Andrew M. D. Richardson , Lancaster University, UK
Ian A. Grout , Lancaster University, UK
Thomas Olbrich , Lancaster University, UK
pp. 511

Hierarchy based Statistical Fault Simulation of Mixed-Signal ICs (Abstract)

Mani Soma , University of Washington, Seattle
Giri Devarayanadurg , University of Washington, Seattle
Prashant Goteti , University of Washington, Seattle
pp. 521

An Integration of Memory-Based Analog Signal Generation Into Current DFT Architectures (Abstract)

Gordon W. Roberts , McGill University, Quebec, CANADA
Evan M. Hawrysh , McGill University, Quebec, CANADA
pp. 528
Session 20.0: DFT: Inching Forward With Partial-Scan Design

null (PDF)

pp. null

Partial Scan Design Based on State Transition Modeling (Abstract)

Vamsi Boppana , University of Illinois, Urbana
W. Kent Fuchs , Purdue University, West Lafayette, IN
pp. 538

A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information (Abstract)

Dong Xiang , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
pp. 548

Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs (Abstract)

Matteo Sonza Reorda , Politecnico di Torino, Italy
Paolo Prinetto , Politecnico di Torino, Italy
Maurizio Rebaudengo , Politecnico di Torino, Italy
Fulvio Corno , Politecnico di Torino, Italy
pp. 558
Session 21.0: Test Languages And Tools

null (PDF)

pp. null

Standard Test Interface Language (STIL) A New Language for Patterns and Waveforms (Abstract)

Gregory A. Maston , Motorola Corporation, AZ
Tony Taylor , Credence Systems Corporation, CA
pp. 565

LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits (Abstract)

Guy Quesnel , Northern Research Ltd. Nepean, Ontario, Canada
Khaled Saab , OPMAX Inc, Montreal, Canada
Naim Ben Hamida , OPMAX Inc, Montreal, Canada
Bozena Kaminska , Ecole Polytechnique of the University of Montreal, Canada
David Marche , Ecole Polytechnique of the University of Montreal, Canada
pp. 571

Developing A Testing Maturity Model For Software Test Process Evaluation And Improvement (Abstract)

Robert Carlson , Illinois Institute of Technology, Chicago
Taratip Suwanassart , Illinois Institute of Technology, Chicago
Ilene Burnstein , Illinois Institute of Technology, Chicago
pp. 581
Session 22.0: Application of SPC to IC Design, Manufacturing And Test

null (PDF)

pp. null

ASIC Yield Estimation At Early Design Cycle (Abstract)

Vonkyoung Kim , Colorado State University, Fort Collins
Mick Tegethoff , Hewlett-Packard Company, Loveland, CO
Tom Chen , Colorado State University, Fort Collins
pp. 590

SPC On The IC-Production Test Process (Abstract)

Ger van Boxem , Philips Semiconductors B.V.
Jos van der Peet , Philips Semiconductors B.V.
pp. 605
Session 23.0: New Techniques For Realistic Faults

null (PDF)

pp. null

Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis (Abstract)

David B. Lavo , Computer Engineering University of California, Santa Cruz
Tracy Larrabee , Computer Engineering University of California, Santa Cruz
Brian Chess , Hewlett-Packard Corporation, Palo Alto, CA
pp. 611

Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation (Abstract)

J. Ferreira , INESC / IST, Portugal
J. P. Teixeira , INESC / IST, Portugal
F. Celeiro , INESC / IST, Portugal
M. B. Santos , INESC / IST, Portugal
L. Dias , INESC / IST, Portugal
pp. 620

Using Target Faults To Detect Non-Target Defects (Abstract)

M. Ray Mercer , Texas A&M University
Li-C Wang , University of Texas at Austin
pp. 629
Session 24: Design-For-Testability Inspirations

null (PDF)

pp. null

A Unifying Methodology For Intellectual Property And Custom Logic Testing (Abstract)

Tushar Gheewala , CrossCheck Technology Inc.
Prab Varma , CrossCheck Technology Inc.
Sandeep Bhatia , CrossCheck Technology Inc.
pp. 639

Constructive Multi-Phase Test Point Insertion for Scan-Based BIST (Abstract)

Nagesh Tamarapalli , McGill University, Montreal. Canada
Janusz Rajski , Mentor Graphics Corp., Wilsonville, OR
pp. 649

Ortohgonal Scan: Low Overhead Scan For Data Paths (Abstract)

Edward J. McCluskey , Stanford University, CA
Robert B. Norwood , Stanford University, CA
pp. 659
Session 25.0: High Frequency And Timing In ATE

null (PDF)

pp. null

An Application of Photoconductive Switch For High-Speed Testing (Abstract)

Kazunori Chihara , ADVANTEST Laboratories Ltd.
Koji Sasaki , ADVANTEST Laboratories Ltd.
Takashi Sekino , ADVANTEST Corp.
pp. 669

Generation Technique of 500MHz Ultra-High Speed Algorithmic Pattern (Abstract)

Toshimi Ohsawa , ADVANTEST Corporation
Hideaki Imada , ADVANTEST Corporation
Masaru Tsuto , ADVANTEST Corporation
Kenichi Fujisaki , ADVANTEST Corporation
pp. 677
Session 26.0: Topics In Test Engineering

null (PDF)

pp. null

Analysis And Detection of Timing Failures In An Experimental Test Chip (Abstract)

Piero Franco , Stanford University, CA
Jonathan Chang , Stanford University, CA
Yi-Chin Chu , Stanford University, CA
William D. Farwell , Hughes Aircraft Company, Los Angeles, CA
E. J. McCluskey , Stanford University, CA
Siyad Ma , Stanford University, CA
Robert L. Stokes , Hughes Aircraft Company, Los Angeles, CA
Sanjay Wattal , Stanford University, CA
pp. 691
Session 27.0: System Test: Practical Aspects, Partitioning And Simulation

null (PDF)

pp. null

Backplane Interconnect Test In A Boundary-Scan Environment (Abstract)

Wuudiann Ke , Lucent Technologies, Princeton, New Jersey
pp. 717

Testability-Oriented Hardware/Software Partitioning (Abstract)

Ghassan Al Hayek , LSR-IMAG, France
Yves Le Traon , LSR-IMAG, France
Chantal Robach , LSR-IMAG, France
pp. 725

System Level Fault Simulation (Abstract)

Isabel Hidalgo , ETSIIyT. University of Cantabria
Pablo S?nchez , ETSIIyT. University of Cantabria
pp. 732
Session 28.0: Test Synthesis Solutions

null (PDF)

pp. null

ASIC BIST Synthesis: A VHDL Approach (Abstract)

Tom Eberle , A Lockheed Martin Company
Bob McVay , A Lockheed Martin Company
Jason Moore , A Lockheed Martin Company
Chris Meyers , A Lockheed Martin Company
pp. 741

Integrating Scan Into Hierarchical Synthesis Methodologies (Abstract)

Markus Robinson , WindRiver Systems, Inc., Alameda, CA
Chris Ellingham , Synopsys, Inc, Mountain View, CA
James Beausang , Synopsys, Inc, Mountain View, CA
pp. 751

Synthesis Of Self-Testing Finite State Machines From High-Level Specification (Abstract)

R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
Vishwani D. Agrawal , Lucent Technologies, Murray Hill, NJ
Maurizio Damiani , Synopsys, Inc., Mountain View, CA
pp. 757
Session 29.0: Advanced Fault Modelling Techniques

null (PDF)

pp. null

Fault Coverage Analysis For Physically-Based CMOS Bridging Faults At Different Power Supply Voltages (Abstract)

Yuyun Liao , Texas A&M University, College Station, TX
D. M. H. Walker , Texas A&M University, College Station, TX
pp. 767

Iddq Test: Sensitivity Analysis of Scaling (Abstract)

R. Kapur , IBM, Mountain View, CA
R. H. Dennard , IBM, Yorktown, New York
M. R. Mercer , Texas A&M, College, TX
T. W. Williams , IBM, Boulder, Colorado
W. Maly , CMU, Pittsburgh, Pennsylvania
pp. 786
Session 30.0: Test Economic Issues

null (PDF)

pp. null

Issues in Optimizing The Test Process - A Telecom Case Study (Abstract)

Brenton White , Hewlett Packard Laboratories, Eugene, OR
Felix Frayman , Hewlett Packard Laboratories, Vancouver, WA
Mick Tegethoff , Hewlett Packard,Loveland, CO
pp. 800

Application of Boundary Scan in a Fault Tolerant Computer System (Abstract)

Peter Dziel , Stratus Computer, Inc., Marlboro, MA
Matthew Boutin , Stratus Computer, Inc., Marlboro, MA
pp. 809
Session 31.0: MCM Test: Methods And Applications

null (PDF)

pp. null

Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates (Abstract)

K. Sasidhar , Georgia Institute of Technology
A. Chatterjee , Georgia Institute of Technology
Y. Zorian , Lucent Bell Laboratories
pp. 818

Three Different MCMs, Three Different Test Strategies (Abstract)

Andrew Flint , Motorola, Incorporated, Austin, Texas
pp. 828

MCM Compute Node Thermal Failure - Design or Test Problem? (Abstract)

Edward P. Sayre , North East Systems Associates, Inc.
pp. 834
Session D1.0: Design Validation: Methodologies And Case Studies

null (PDF)

pp. null

Commercial Design Verification: Methodology and Tools (Abstract)

Jun Yuan , Motorola, Inc., Austin, TX
W. C. Bruce , Motorola, Inc., Austin, TX
Jaehong Park , Motorola, Inc., Austin, TX
Michael Burns , Motorola, Inc., Austin, TX
Janet Nguyen , Motorola, Inc., Austin, TX
Jai Kumar , Motorola, Inc., Austin, TX
Kurt Shultz , Motorola, Inc., Austin, TX
Carl Pixley , Motorola, Inc., Austin, TX
Matt Kaufmann , Motorola, Inc., Austin, TX
Noel R. Strader , Motorola, Inc., Austin, TX
pp. 839

PowerPC<sup>TM</sup> Array Verification Methodology Using Formal Techniques (Abstract)

Neeta Ganguly , Motorola Inc, Austin, TX
Manish Pandey , Motorola Inc, Austin, TX
Magdy Abadir , Motorola Inc, Austin, TX
pp. 857
Session D2.0: Hybrid Validation And Test Techniques

null (PDF)

pp. null

An ATPG-Based Framework for Verifying Sequential Equivalence (Abstract)

Uwe Glaeser , The German National Research
Shi-Yu Huang , University of California, Santa Barbara
Kuang-Chien Chen , Fujitsu Labs. of America
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 865

A Unified Framework for Design Validation and Manufacturing Test (Abstract)

Jacob A. Abraham , University of Texas at Austin, TX
Yatin V. Hoskote , University of Texas at Austin, TX
Dinos Moundanos , University of Texas at Austin, TX
pp. 875
Session D3.0: Design Validation: From System Specification to Process Effects

null (PDF)

pp. null

Testing-Based Analysis of Real-Time System Models (Abstract)

Insup Lee , University of Pennsylvania, Philadelphia
Duncan Clarke , University of Pennsylvania, Philadelphia
pp. 894

Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor (Abstract)

Nirmal R. Saxena , HaL Computer Systems, Campbell, CA
Irith Pomeranz , University of Iowa, Iowa City
Yan A. Li , HaL Computer Systems, Campbell, CA
Richard Reeve , HaL Computer Systems, Campbell, CA
Paritosh Kulkarni , HaL Computer Systems, Campbell, CA
pp. 904

Process Aggravated Noise (PAN): New Validation and Test Problems (Abstract)

Melvin A. Breuer , University of Southern California, Los Angeles
Sandeep K. Gupta , University of Southern California, Los Angeles
pp. 914
Session L1: Unpowered Opens Testing

null (PDF)

pp. null

ITC 1996 Lecture Series on Unpowered Opens Testing (PDF)

Kenneth P. Parker , Hewlett Packard Manufacturing Test Division, Loveland, CO
pp. 924

Capacitive Leadframe Testing (PDF)

Ted T. Turner , Hewlett-Packard Company
pp. 925

Unpowered Opens Test with X-Ray Laminography (PDF)

Stig Oresjo , Hewlett-Packard Company, Loveland, Colorado
pp. 929
Session L2: Practical Aspects of IC Diagnosis & Failure Analysis: A Walk Through The Process

null (PDF)

pp. null

An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics (PDF)

David P. Vallett , IBM Microelectronics Division, Essex Junction, Vermont
pp. 930

Modelling the Unmodellable: Algorithmic Fault Diagnosis (PDF)

Robert C. Aitken , Hewlett Packard Co., Palo Alto, CA
pp. 931

Shmoo Plotting : The Black Art of IC Testing (PDF)

Keith Baker , Philips ED&T, Eindhoven, The Netherlands
Jos van Beers , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 932

Integrating Automated Diagnosis Into The Testing And Failure Analysis Operations (PDF)

Anjali Jones , Texas Instruments Incorporated, Stafford, TX
Kenneth M. Butler , Texas Instruments Incorporated, Dallas, TX
Jeff Platt , Texas Instruments Incorporated, Stafford, TX
Karl Johnson , Texas Instruments Incorporated, Stafford, TX
Jayashree Saxena , Texas Instruments Incorporated, Dallas, TX
pp. 934

IC Failure Analysis Tools and Techniques - Magic, Mystery, and Science (PDF)

Christopher L. Henderson , Sandia National Laboratories, Albuquerque, NM
Richard E. Anderson , Sandia National Laboratories, Albuquerque, NM
Jerry M. Soden , Sandia National Laboratories, Albuquerque, NM
pp. 935
Panel 1: Why Do We Talk About DFT When The Problem Is Bad Design And Bad CAD Tools

null (PDF)

pp. null

The Key to Concurrent Engineering is Design Tools (PDF)

William R. Simpson , Institute for Defense Analyses
pp. 937
Panel 2: Asynchronous Design: Nightmare or Opportunity?

null (PDF)

pp. null

The Return of Asynchronous Logic (PDF)

S. B. Furber , The University of Manchester, Oxford Road, UK
pp. 938

Asynchronous Design: Working The Fast Lane (PDF)

Marly Roncken , Philips Research Laboratories, The Netherlands
pp. 939
Panel 5: DFT For Embedded Cores

null (PDF)

pp. null
Panel 6: What Are The Next Generation Test Methodologies For Board And System Test?

null (PDF)

pp. null

The Need for Complete System Level Test Standardization (PDF)

Peter Dziel , Stratus Computer, Inc., Marlboro, MA
pp. 941
Panel 7: Will I<sub>DDQ</sub> Testing Leak Away In Deep Sub-Micron Technology?

null (PDF)

pp. null

Deep Sub-micron I<sub>DDQ</sub> Test Options (PDF)

Manoj Sachdev , Philips Research Laboratories, The Netherlands
pp. 942
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