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2010 IEEE Computer Society Annual Symposium on VLSI (2010)
Lixouri, Cephalonia Greece
July 5, 2010 to July 7, 2010
ISBN: 978-0-7695-4076-4
pp: 416-421
ABSTRACT
This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.
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CITATION

R. Knopp, E. Amador, R. Pacalet and V. Rezard, "Dynamic Power Management on LDPC Decoders," 2010 IEEE Computer Society Annual Symposium on VLSI(VLSID), Lixouri, Cephalonia Greece, 2010, pp. 416-421.
doi:10.1109/ISVLSI.2010.70
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