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2010 IEEE Computer Society Annual Symposium on VLSI (2010)
Lixouri, Cephalonia Greece
July 5, 2010 to July 7, 2010
ISBN: 978-0-7695-4076-4
pp: 69-73
ABSTRACT
This work introduces a new technique to improve the global placement, which can be applied to any regular placer. We propose an algorithm called Logical Core, based on Google PageRankâ, which distributes probability weights to every cell in the circuit netlist. Then, these weights are used to select the most important cells for the global placement. By using this information, we are able to improve global placement in terms of wirelength. The Logical Core algorithm proposes a new complexity rule to the placement graph. This complexity has a great similarity with the Rent’s Rule. The technique improves the total wirelength in all tested cases by 4.5%.
INDEX TERMS
Placement, Complexity, Controllability, Physical Design, Algorithms and Microelectronics
CITATION

L. Cavalheiro, F. Pinto, R. Reis and M. Johann, "Logical Core Algorithm: Improving Global Placement," 2010 IEEE Computer Society Annual Symposium on VLSI(VLSID), Lixouri, Cephalonia Greece, 2010, pp. 69-73.
doi:10.1109/ISVLSI.2010.114
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