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2009 IEEE Computer Society Annual Symposium on VLSI (2009)
Tampa, Florida
May 13, 2009 to May 15, 2009
ISBN: 978-0-7695-3684-2
pp: 67-72
In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different number of DCT coefficients in the zig-zag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose a configuration manager which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use LZSS algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve 400 MBytes/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration.
DCT, dynamic partial reconfiguration, self reconfigurable, compression, FPGA

J. Huang and J. Lee, "A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching," 2009 IEEE Computer Society Annual Symposium on VLSI(VLSID), Tampa, Florida, 2009, pp. 67-72.
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