2009 IEEE Computer Society Annual Symposium on VLSI (2009)
May 13, 2009 to May 15, 2009
Die stacking is a promising new technology that enables integration of devices in the third dimension. It allows the stacking of multiple active layers directly on top of one another with short, dense die-to-die vias providing communication. Previous work has shown significant benefits at all design targets, from stacking memory on logic to partitioning individual architectural units across multiple layers. Many high-speed processor units-ALUs, register files, caches, and instruction schedulers-have all been designed in 3D, achieving significant, simultaneous power savings and performance boosts. Other work has looked at the implementation of network-on-chip in a die stack but restricted the focus to planar designs of the various unit(processors, routers, etc.). This work follows up on these two re-search areas to explore the 3D design of router components, specifically the crossbar. We examine the implementation of a crossbar and two multistage interconnect networks to determine the potential benefits of 3D implementations. Compared to equivalent planar designs,we achieve a maximum delay reduction of 26% and maximum power savings of 24%.
integrated circuit design, integrated circuit interconnections
D. L. Lewis, S. Yalamanchili and H. S. Lee, "High Performance Non-blocking Switch Design in 3D Die-Stacking Technology," 2009 IEEE Computer Society Annual Symposium on VLSI(VLSID), Tampa, Florida, 2009, pp. 25-30.