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2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2018)
Hong Kong
Jul 8, 2018 to Jul 11, 2018
ISSN: 2159-3477
ISBN: 978-1-5386-7099-6
pp: 263-268
ABSTRACT
In this paper we discuss the potential foundry announced hybrid integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FD-SOI) technology. The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next generation voltage-controlled magnetic anisotropy (VCMA) MTJ are separately integrated into a 28 nm FD-SOI process. Circuit-level design strategies are explored that use FD-SOI leverage and spin-device characteristic to realize writing and reading power-delay efficiency, robust and reliable performance in a 1-transistor 1-MTJ (1T1M) bit cell. Process variation aware strategies for MTJ-FDSOI integration are proposed to compensate failure operations, by using the dynamic step-wise back-bias and the flip-well back-bias. A qualitative summary demonstrates that the MRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.
INDEX TERMS
CMOS memory circuits, magnetic anisotropy, magnetic tunnelling, MRAM devices, silicon-on-insulator
CITATION

H. Cai et al., "MRAM-on-FDSOI Integration: A Bit-Cell Perspective," 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, 2018, pp. 263-268.
doi:10.1109/ISVLSI.2018.00056
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