2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2018)
Jul 8, 2018 to Jul 11, 2018
This paper proposes a fully-on-chip mixed-mode low-dropout (LDO) regulator with regulation and transient response enhanced. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. With the help of the digital regulation part, the supported maximum load current is significantly improved. The proof-of-concept LDO design is fabricated in a standard 0.18-mm CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA.
CMOS integrated circuits, integrated circuit design, integrated circuit manufacture, load regulation, transient response, voltage regulators
H. Li, C. Zhan and N. Zhang, "Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses," 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, 2018, pp. 160-163.