A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2017)
Bochum, Northrhine Westfalia, Germany
July 3, 2017 to July 5, 2017
In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further power reduction. The proposed ADC is designed in UMC 0.18um CMOS technology with a supply voltage of 1.8V and simulated in Cadence Spectre Simulator. The ADC achieves 9.5 bit accuracy with 59.44dB SNR and 70.92dB SFDR and dissipates 4.36mW power. The proposed ADC has better FOM compared to that reported in the literature.
Capacitors, Switches, Capacitance, Power demand, Topology, Power dissipation, Clocks
G. R, A. V. K and B. Venkataramani, "A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology," 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Northrhine Westfalia, Germany, 2017, pp. 594-599.