2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2017)
Bochum, Northrhine Westfalia, Germany
July 3, 2017 to July 5, 2017
As the power wall has become one of the main limiting factors for the performance of general purpose processors, the trend in High Performance Computing (HPC) is moving towards application-specific accelerators in order to meet the stringent performance requirements for exascale computing while still satisfying power budget constraints. Within this context, reconfigurable devices, and more specifically FPGA-based systems, represent a promising solution able to achieve highly energy efficient computations without jeopardizing performance. Nevertheless, the exploitation of reconfigurable hardware is still limited due to the hardware-software co-design challenges that it poses, the time consuming design space exploration process and the programming complexity. To overcome these challenges, the EXTRA European project addresses the reconfigurability of such devices as a first-class feature, covering the entire stack from the system architecture up to the application. Within this paper, we present the effort of the EXTRA project towards the definition of an adaptive open platform for the optimization and implementation of applications on high performance reconfigurable architectures. The underlying infrastructure of the platform is here presented, highlighting its capability to integrate modules from different developers in order to stimulate external contributions and open research.
Field programmable gate arrays, Runtime, Tools, Hardware, Optimization, Acceleration, Computer architecture
M. Rabozzi et al., "A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project," 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Northrhine Westfalia, Germany, 2017, pp. 368-373.