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2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2014)
Tampa, FL, USA
July 9, 2014 to July 11, 2014
ISBN: 978-1-4799-3763-9
pp: 332-337
This paper presents a dynamically configurable and area-efficient multi-precision architecture for Floating Point (FP) division. FP division is a core arithmetic in scientific and engineering domain. We propose an architecture for double precision (DP) division which is also capable of processing dual (two-parallel) single precision (SP) computation, named as DPdSP FP divider. The architecture is based on series expansion methodology ofcomputing division. Key components involved in the floatingpoint division architecture are re-designed in order to efficiently enable the resource sharing and tune the data-path for processing both precision operands with minimum hardware overhead. We have targeted the proposed architecture using "OSUcells Cell Library" 0.18μm technology ASIC implementation. Compared to a standalone double precision divider, the proposed dual modeunified architecture needs ≈ 7% extra hardware, with ≈ 5% delay overhead. When compared to the previous work in literature, the proposed dual mode architecture out-perform them in terms of required area, throughput, and area × delay, has smaller area & delay overhead over only DP divider, and has more computational support.
Adders, Delays, Multiplexing, Table lookup, Hardware, Data mining,Dynamic Configurable Computing, Floating Point Division, ASIC, Multi-precision Arithmetic
Manish Kumar Jaiswal, Ray C.C. Cheung, M. Balakrishnan, Kolin Paul, "Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division", 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), vol. 00, no. , pp. 332-337, 2014, doi:10.1109/ISVLSI.2014.45
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