The Community for Technology Leaders
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2007)
Porto Alegre, Brazil
Mar. 9, 2007 to Mar. 11, 2007
ISBN: 0-7695-2896-1
TABLE OF CONTENTS
Introduction

Reviewer List (PDF)

pp. xv
MPSOC

Overview of the Scalable Communications Core (Abstract)

Aliaksei Chapyzhenka , Intel Corporation
David Arditti Ilitzky , Intel Corporation
Jeff Hoffman , Intel Corporation
Anthony Chun , Intel Corporation
pp. 3-8

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design (Abstract)

Nacer-Eddine Zergainoh , TIMA Labs, Grenoble Universities, France
Youssef Atat , TIMA Labs, Grenoble Universities, France
pp. 9-14

A Flexible Datapath Interconnect for Embedded Applications (Abstract)

Magnus Sjalander , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
Magnus Bjork , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
Per Larsson-Edefors , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
pp. 15-20

HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems (Abstract)

Lionel Torres , LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
Nicolas Saint-Jean , LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
Gilles Sassatelli , LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
Michel Robert , LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
Pascal Benoit , LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
pp. 21-28
Reconfigurable Systems

Technological hybridization for efficient runtime reconfigurable FPGAs (Abstract)

L. Torres , University of Montpellier 2, Montpellier Cedex 5, France
G. Sassatelli , University of Montpellier 2, Montpellier Cedex 5, France
N. Bruchon , University of Montpellier 2, Montpellier Cedex 5, France
G. Cambon , University of Montpellier 2, Montpellier Cedex 5, France
pp. 29-34

Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC (Abstract)

Elmar U. K. Melcher , Universitaet Karlsruhe (TH), Germany
Alisson V. Brito , Universitaet Karlsruhe (TH), Germany
Jurgen Becker , Universitaet Karlsruhe (TH), Germany
Michael Hubner , Universitaet Karlsruhe (TH), Germany
Matthias Kuhnle , Universitaet Karlsruhe (TH), Germany
pp. 35-40

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs (Abstract)

Jurgen Becker , Universitat Karlsruhe (TH), Germany
Lars Braun , Universitat Karlsruhe (TH), Germany
Christopher Claus , Munich University of Technology
Walter Stechele , Munich University of Technology
Michael Hubner , Universitat Karlsruhe (TH), Germany
pp. 41-46

Transparent Dataflow Execution for Embedded Applications (Abstract)

Antonio Carlos S. Beck , Universidade Federal do Rio Grande do Sul, Brazil
Mateus B. Rutzig , Universidade Federal do Rio Grande do Sul, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
pp. 47-54
Methods for Optimized Placement

A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs (Abstract)

Dimitrios Soudris , Democritus University of Thrace, Xanthi, Greece
Kostas Siozios , Democritus University of Thrace, Xanthi, Greece
pp. 55-60

A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures (Abstract)

Tiago Teixeira , Universidade Federal de Vicosa, Brazil
Joao M. P. Cardoso , INESC-ID/IST/UTL, Portugal
Ricardo Ferreira , Universidade Federal de Vicosa, Brazil
Alisson Garcia , Universidade Federal de Vicosa, Brazil
pp. 61-66

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits (Abstract)

Guilherme Flach , UFRGS - Universidade Federal do Rio Grande do Sul, Brazil
Ricardo Reis , UFRGS - Universidade Federal do Rio Grande do Sul, Brazil
Felipe Pinto , UFRGS - Universidade Federal do Rio Grande do Sul, Brazil
Renato Hentschke , UFRGS - Universidade Federal do Rio Grande do Sul, Brazil
pp. 67-72

Minimum-Congestion Placement for Y-interconnects: Some studies and observations (Abstract)

Parthasarathi Dasgupta , Bengal Engineering & Science University, Howrah, India
Tuhina Samanta , Bengal Engineering & Science University, Howrah, India
Hafizur Rahaman , Bengal Engineering & Science University, Howrah, India
Prasun Ghosal , Bengal Engineering & Science University, Howrah, India
pp. 73-80
VLSI System Design, Methods and Tools

Design of a MCML Gate Library Applying Multiobjective Optimization (Abstract)

Pablo Alvarado-Moya , Costa Rica Institute of Technology, Costa Rica
Wolfgang H. Krautschneider , Costa Rica Institute of Technology, Costa Rica
Roberto Pereira-Arroyo , Costa Rica Institute of Technology, Costa Rica
pp. 81-85

Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations (Abstract)

Lucas Brusamarello , Institute de InformAtica - UFRGS
Roberto Da Silva , Institute de InformAtica - UFRGS
Gilson I. Wirth , UFRGS, Brazil
Ricardo A.L. Reis , Institute de InformAtica - UFRGS
pp. 86-91

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis (Abstract)

Fabrizio Ferrandi , DEI - Politecnico di Milano, Italy
Davide Pandini , STMicroelectronics
Donatella Sciuto , DEI - Politecnico di Milano, Italy
Angelo P. E. Rosiello , DEI - Politecnico di Milano, Italy
pp. 92-97

Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications (Abstract)

Wei-Chien Tang , National Central University, Jhongli, Taiwan
Chin-Long Wey , National Central University, Jhongli, Taiwan
Shin-Yo Lin , National Central University, Jhongli, Taiwan
pp. 98-106
Methods for Low Power Design I

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing (Abstract)

Yasuhiro Morita , Kobe University
Koji Nii , Renesas Technology Corporation, 4-1 Mizuhara, Itami 664-0005, Japan
Hidehiro Fujiwara , Kobe University
Hiroki Noguchi , Kobe University
Masahiko Yoshimoto , Kobe University, 1-1 Rokkodai, Nada, Kobe, Hyogo 657-8501, Japan
Yusuke Iguchi , Kobe University
Hiroshi Kawaguchi , Kobe University, 1-1 Rokkodai, Nada, Kobe, Hyogo 657-8501, Japan
pp. 107-112

Design and Analysis of Low Power Dynamic Bus Based on RLC simulation (Abstract)

Shanq-Jang Ruan , National Taiwan University of Science and Technology
Yu-Ting Pai , National Taiwan University of Science and Technology
Shang-Fang Tsai , National Taiwan University of Science and Technology
pp. 113-118

Interconnect Power Optimization Based on Timing Analysis (Abstract)

Yuchun Ma , Tsinghua University, Beijing
Liu Yang , Tsinghua University, Beijing
Sheqin Dong , Tsinghua University, Beijing
Xianlong Hong , Tsinghua University, Beijing
pp. 119-124

Overdrive Power-Gating Techniques for Total Power Minimization (Abstract)

Per Larsson-Edefors , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
Lars "J" Svensson , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
Mindaugas Dra?zd?ziulis , Chalmers University of Technology, SE-412 96 G?oteborg, Sweden
pp. 125-132
Mixed Signal Design

Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured Results (Abstract)

Patrick Wolf , Duke University
Thomas Jochum , Duke University
Nikolaus Klemmer , Ericsson Mobile Platforms
Himanshu Arora , Marvell Semiconductor
pp. 133-138

Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers (Abstract)

Yehia Massoud , Rice University, Houston, Texas
Tamer Ragheb , Rice University, Houston, Texas
Arthur Nieuwoudt , Rice University, Houston, Texas
pp. 139-144

An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms (Abstract)

Ranga Vemuri , University of Cincinnati
Angan Das , University of Cincinnati
pp. 145-152
Verification and Test Methodology I

Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor (PDF)

Rajesh Thirugnanam , Virginia Tech, Blacksburg, VA
T. M. Mak , Research Scientist Test Technology Research, Santa Clara, CA
Dong Sam Ha , Virginia Tech, Blacksburg, VA
pp. 153-158

Coverage Driven Verification applied to Embedded Software (Abstract)

Axel Braun , University of Tubingen
Markus Winterholer , Cadence Design Systems
Djones Lettnin , University of Tubingen
Jurgen Ruf , University of Tubingen
Thomas Kropf , University of Tubingen
Joachim Gerlach , University of Tubingen
Wolfgang Rosenstiel , University of Tubingen
pp. 159-164

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation (Abstract)

Rolf Drechsler , University of Bremen, 28359 Bremen, Germany
Ulrich Kuhne , University of Bremen, 28359 Bremen, Germany
Daniel Grobe , University of Bremen, 28359 Bremen, Germany
pp. 165-170

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis (Abstract)

Sravan Kumar Bhaskarani , STMicroelectronics India Pvt Ltd., India
Akhil Garg , STMicroelectronics India Pvt Ltd., India
Prashant Dubey , STMicroelectronics India Pvt Ltd., India
pp. 171-178
Verification and Test Methodology II

A New Test Data Compression Scheme for Multi-scan Designs (Abstract)

Jianhua Feng , Peking University
Teng Lin , Peking University
Yangyuan Wang , Peking University
pp. 179-185

On the Compressibility of Power Grid Models (Abstract)

Joao M. S. Silva , Technical University of Lisbon
L. Miguel Silveira , Technical University of Lisbon
pp. 186-191

Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation (Abstract)

Marcelo S. Lubaszewski , Universidade Federal do Rio Grande do Sul, Brazil
Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, Brazil
M. Renovell , LIRMM - Montpelier - France
Tiago R. Balen , Universidade Federal do Rio Grande do Sul, Brazil
pp. 192-197

Code-coverage Based Test Vector Generation for SystemC Designs (Abstract)

Diogenes Junior Cecilio da Silva , Universidade Federal de Minas Gerais, Brazil
Alair Dias Junior , Universidade Federal de Minas Gerais, Brazil
pp. 198-206
Physical Design I

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits (Abstract)

J. Freijedo , IST (TUL) / INESC-ID Lisboa
I. C. Teixeira , IST (TUL) / INESC-ID Lisboa
J. P. Teixeira , IST (TUL) / INESC-ID Lisboa
J.J. Rodr?guez Andina , Univ. of Vigo
M. B. Santos , IST (TUL) / INESC-ID Lisboa
J. Semiao , Univ. of Algarve
F. Vargas , PUCRS, Brazil
pp. 207-212

Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks (Abstract)

Taraneh Taghavi , University of California, Los Angeles
Majid Sarrafzadeh , University of California, Los Angeles
pp. 213-218

An Efficient Analytical Approach to Path-Based Buffer Insertion (Abstract)

Hamid Reza Kheirabadib , Amirkabir University of Technology, Tehran, Iran
Mehdi Saeedi , Amirkabir University of Technology, Tehran, Iran
Morteza Saheb Zamani , Amirkabir University of Technology, Tehran, Iran
pp. 219-224

Integrated Gate and Wire Sizing at Post Layout Level (Abstract)

Narender Hanchate , University of South Florida, Tampa
Nagarajan Ranganathan , University of South Florida, Tampa
pp. 225-232
Physical Design II

Generating Realistic Stimuli for Accurate Power Grid Analysis (Abstract)

Paulo F. Flores , IST - Technical Univ. of Lisbon
L. Miguel Silveira , IST - Technical Univ. of Lisbon
P. Marques Morgado , IST - Technical Univ. of Lisbon
pp. 233-238

CMP-aware Maze Routing Algorithm for Yield Enhancement (Abstract)

Xianlong Hong , Tsinghua University, Beijing
Yici Cai , Tsinghua University, Beijing
Hailong Yao , Tsinghua University, Beijing
pp. 239-244

Statistical Gate Sizing for Yield Enhancement at Post Layout Level (Abstract)

Nagarajan Ranganathan , University of South Florida, Tampa, FL
Narender Hanchate , University of South Florida, Tampa, FL
pp. 245-252
SoC Embedded Processing

Automatic Retargeting of Binary Utilities for Embedded Code Generation (Abstract)

Olinto Furtado , Federal University of Santa Catarina
Paulo Centoducatte , State University of Campinas
Alexandro Baldassin , State University of Campinas
Luiz C. V. Santos , Federal University of Santa Catarina
Sandro Rigo , State University of Campinas
Max Schultz , Federal University of Santa Catarina
Daniel Casarotto , Federal University of Santa Catarina
pp. 253-258

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors (Abstract)

Thomas Wild , Munich University of Technology, Arcisstr
Andreas Herkersdorf , Munich University of Technology, Arcisstr
Rainer Ohlendorf , Munich University of Technology, Arcisstr
Michael Meitinger , Munich University of Technology, Arcisstr
pp. 259-264
VLSI Circuits

High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit (Abstract)

Rong Luo , Tsinghua University
Saihua Lin , Tsinghua University
Huazhong Yang , Tsinghua University
pp. 273-278

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan (Abstract)

Jinian Bian , Tsinghua University
Qiang Zhou , Tsinghua University
Zhipeng Liu , Tsinghua University
Hui Dai , Tsinghua University
pp. 279-284

Design of a Novel CNTFET-based Reconfigurable Logic Gate (Abstract)

D. Navarro , Institut des Nanotechnologies de Lyon (INL), France
J. Liu , Institut des Nanotechnologies de Lyon (INL), France
I. O?Connor , Institut des Nanotechnologies de Lyon (INL), France
F. Gaffiot , Institut des Nanotechnologies de Lyon (INL), France
pp. 285-290

Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs (Abstract)

Ranga Vemuri , University of Cincinnati, Cincinnati, Ohio, USA
Shubhankar Basu , University of Cincinnati, Cincinnati, Ohio, USA
pp. 291-298
NoC

Inserting Data Encoding Techniques into NoC-Based Systems (Abstract)

Leandro Soares null , IndrusiakMES -TU Darmstadt
Fernando G. Moraes , PPGCC - FACIN - PUCRS
Manfred Glesner , MES - TU Darmstadt
Jos? C. S. Palma , PPGC - II - UFRGS - Av.
Alberto Garcia Ortiz , MES - TU Darmstadt
Ricardo A. L. Reis , PPGC - II - UFRGS - Av.
pp. 299-304

Performance Evaluation for Three-Dimensional Networks-On-Chip (Abstract)

Partha Pratim Pande , Washington State University
Brett Feero , Washington State University
pp. 305-310

Application - specific NoC platform design based on System Level Optimization (Abstract)

L. Papadopoulos , Democritus Univ. Thrace, 67100 Xanthi, Greece.
D. Soudris , Democritus Univ. Thrace, 67100 Xanthi, Greece
F. Catthoor , Katholieke Univ. Leuven, Belgium.
S. Mamagkakis , IMEC, Kapeldreef 75, 3001 Heverlee, Belgium.
pp. 311-316

Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding (Abstract)

Partha Pratim Pande , Washington State University
Amlan Ganguly , Washington State University
Cristian Grecu , University of British Columbia
Benjamin Belzer , Washington State University
pp. 317-324
IP and Design, VLSI System Design

Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding (Abstract)

Naofal Al-Dhahir , University of Texas at Dallas
Dake Liu , Linkoping University
Di Wu , Linkoping University
Johan Eilert , Linkoping University
Hlaing Minn , University of Texas at Dallas
Dandan Wang , University of Texas at Dallas
pp. 325-330

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs (Abstract)

Gianluca Palermo , Politecnico di Milano, Italy
Fabrizio Ferrandi , Politecnico di Milano, Italy
Antonino Tumeo , Politecnico di Milano, Italy
Matteo Monchiero , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
pp. 331-336

Partial Product Reduction for Parallel Cubing (Abstract)

James E. Stine , Oklahoma State University
Jeff M. Blank , Oklahoma State University
pp. 337-342

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format (Abstract)

M.Kirthi Krishna , International Institute of Information Technology, India
Sreehari Veeramachaneni , International Institute of Information Technology, India
M.B. Srinivas , International Institute of Information Technology, India
Lingamneni Avinash , International Institute of Information Technology, India
Reddy P Sreekanth , International Institute of Information Technology, India
pp. 343-350
System Level Design

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation (Abstract)

Guido Araujo , State University of Campinas, Brazil
Sandro Rigo , State University of Campinas, Brazil
Rodolfo Azevedo , State University of Campinas, Brazil
Bruno Albertini , State University of Campinas, Brazil
Richard Maciel , State University of Campinas, Brazil
pp. 351-356

Designing Memory Subsystems Resilient to Process Variations (Abstract)

Mahmoud Bennaser , University of Massachusetts
Csaba Andras Mortiz , University of Massachusetts
Yao Guo , University of Massachusetts
pp. 357-363

Asymmetrically Banked Value-Aware Register Files (Abstract)

Sotirios G. Ziavras , New Jersey Institute of Technology
Shuai Wang , New Jersey Institute of Technology
Hongyan Yang , New Jersey Institute of Technology
Jie Hu , New Jersey Institute of Technology
pp. 363-368

A MEMS Ultra-Stable Short Duration Current Pulse Generator (Abstract)

Andrew Tam , University of Windsor, Canada
Sazzadur Chowdhury , University of Windsor, Canada
pp. 369-374

Investigating Simple Low Latency Reliable Multiported Register Files (Abstract)

Madhu Mutyam , International Institute of Information Technology, India
N. Vijaykrishnan , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
Andrew J. Ricketts , Pennsylvania State University
pp. 375-382
Methods for Low Power Design II

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction (Abstract)

Yici Cai , Tsinghua University
Xianlong Hong , Tsinghua University
Jiang Hu , Texas A&M University
Weixiang Shen , Tsinghua University
pp. 383-388

A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs (Abstract)

Srinivasa R. STG , MG-I, Intel Technology (I)(P) Ltd., India
Prashant Agrawal , CSE, Indian Institute of Technology
Saurabh Vijay , MG-I, Intel Technology (I)(P) Ltd., India
Ajit N. Oke , MG-I, Intel Technology (I)(P) Ltd., India
pp. 389-394

On the Limitations of Power Macromodeling Techniques (Abstract)

Roberto Leao , UFSC, Brazil
Luiz C. V. Dos Santos , UFSC, Brazil
Guido Araujo , Institute of Computing, UNICAMP, Brazil
Rodolfo Azevedo , Institute of Computing, UNICAMP, Brazil
Felipe Klein , Institute of Computing, UNICAMP, Brazil
pp. 395-400

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme (Abstract)

M B Srinivas , International Institute of Information Technology (IIIT), Hyderabad, India
C Raghunandan , International Institute of Information Technology (IIIT), Hyderabad, India
K S Sainarayanan , International Institute of Information Technology (IIIT), Hyderabad, India
pp. 401-408
Emerging Trends in VLSI

Performance of Graceful Degradation for Cache Faults (Abstract)

Bruce R. Childers , Univ. of Pittsburgh
Hyunjin Lee , Univ. of Pittsburgh
Sangyeun Cho , Univ. of Pittsburgh
pp. 409-415

A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions (Abstract)

D. Voudouris , National Technical University of Athens
M. Sampson , National Technical University of Athens
G. Papakonstantinou , National Technical University of Athens
pp. 416-421

Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets (Abstract)

Mehrdad Najibi , Amirkabir University of Technology, Iran
Mahtab Niknahad , Amirkabir University of Technology, Iran
Hossein Pedram , Amirkabir University of Technology, Iran
pp. 422-427

On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement (Abstract)

Mehdi Sedighi , Amirkabir University of Technology, Iran
Mehdi Saeedi , Amirkabir University of Technology, Iran
Morteza Saheb Zamani , Amirkabir University of Technology, Iran
pp. 428-436
Poster Session I

FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline (Abstract)

Abdel Ejnioui , University of South Florida
pp. 437-438

A Novel Reconfigurable Computation Unit for DSP Applications (Abstract)

Yun-Lung Lee , National Cheng Kung University, Taiwan
Jer Min Jou , National Cheng Kung University, Taiwan
Chen-Yen Lin , National Cheng Kung University, Taiwan
Chien-Ming Sun , National Cheng Kung University, Taiwan
pp. 439-444

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder (Abstract)

Luciano Agostini , UFRGS - Porto Alegre, RS, Brazil
Arnaldo Azevedo , UFRGS - Porto Alegre, RS, Brazil
Bruno Zatt , UFRGS - Porto Alegre, RS, Brazil
Altamiro Susin , UFRGS - Porto Alegre, RS, Brazil
Sergio Bampi , UFRGS - Porto Alegre, RS, Brazil
pp. 445-446

Vector Processing Support for FPGA-Oriented High Performance Applications (Abstract)

Shuai Wang , New Jersey Institute of Technology
Hongyan Yang , New Jersey Institute of Technology
Sotirios G. Ziavras , New Jersey Institute of Technology
Jie Hu , New Jersey Institute of Technology
pp. 447-448

An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb (Abstract)

Matteo Monchiero , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
Fabrizio Ferrandi , Politecnico di Milano, Italy
Antonino Tumeo , Politecnico di Milano, Italy
Gianluca Palermo , Politecnico di Milano, Italy
pp. 449-450

MOTIM - A Scalable Architecture for Ethernet Switches (Abstract)

Daniel Pigatto , DATACOM TELEMATICA, Brazil
Ney Calazans , PUCRS - FACIN, Brazil
Fernando Moraes , PUCRS - FACIN, Brazil
Everton Carara , PUCRS - FACIN, Brazil
?rico Bastos , PUCRS - FACIN, Brazil
pp. 451-452

Toward Memory-efficient Design of Video Encoders for Multimedia Applications (Abstract)

Jayanta Mukherjee , IIT Kharagpur, WB, India
Santosh Ghosh , IIT Kharagpur, WB, India
Avishek Saha , IIT Kharagpur, WB, India
Shamik Sural , IIT Kharagpur, WB, India
pp. 453-454

MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems (Abstract)

Karen A. Tomko , University of Cincinnati, Cincinnati OH
Vijay Swaminathan , University of Cincinnati, Cincinnati OH
Arun Janarthanan , University of Cincinnati, Cincinnati OH
pp. 455-456

Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System (Abstract)

M. Morandi , DEI - Politecnico di Milano
S. Corbetta , DEI - Politecnico di Milano
F. Ferrandi , DEI - Politecnico di Milano
D. Sciuto , DEI - Politecnico di Milano
M. Novati , DEI - Politecnico di Milano
M.D. Santambrogio , DEI - Politecnico di Milano
pp. 457-458

Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload (Abstract)

Ewerson , PUCRS - FACIN, Brazil
Ney Calazans , PUCRS - FACIN, Brazil
Fernando Moraes , PUCRS - FACIN, Brazil
pp. 459-460

High Level RTOS Scheduler Modeling for a Fast Design Validation (Abstract)

C?sar Marcon , PPGCC - FACIN - PUCRS - Porto Alegre, RS - Brazil
Tatiana Santos , PPGCC - FACIN - PUCRS - Porto Alegre, RS - Brazil
Fabiano Hessel , PPGCC - FACIN - PUCRS - Porto Alegre, RS - Brazil
pp. 461-466

A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator (Abstract)

Sergio Bampi , Federal University of Rio Grande do Sul - UFRGS
Eric Fabris , Federal University of Rio Grande do Sul - UFRGS
Luciano Severino de Paula , Federal University of Rio Grande do Sul - UFRGS
Altamiro Amadeu Susin , Federal University of Rio Grande do Sul - UFRGS
pp. 467-470
Poster Session II

A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation (Abstract)

Mahtab Niknahad , Amirkabir University of Technology, Iran
Behnam Ghavami , Amirkabir University of Technology, Iran
Hossein Pedram , Amirkabir University of Technology, Iran
Mehrdad Najibi , Amirkabir University of Technology, Iran
pp. 471-472

Power andPerformance Analysis for Early Design Space Exploration (Abstract)

Tom Chen , Colorado State University
Charles Thangaraj , Colorado State University
pp. 473-478

Reliable Binary Signed Digit Number Adder Design (Abstract)

F. Kharbash , University of Missouri-Kansas City
G. M. Chaudhry , University of Missouri-Kansas City
pp. 479-484

Voltage Pump Based on Self Clocked Cells (Abstract)

Hector Kirschenbaum , University of Buenos Aires
Alejandro De la Plaza , University of Buenos Aires
pp. 485-487

Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks (Abstract)

Ali Afzali-Kusha , University of Tehran, Iran
Masoud Rostami , University of Tehran, Iran
Mohammad Azim Karami , University of Tehran, Iran
Reza Faraji-Dana , University of Tehran, Iran
pp. 488-489

Subthreshold Pass Transistor Logic for Ultra-Low Power Operation (Abstract)

Ali Afzali-Kusha , University of Tehran, Tehran, Iran
Vahid , University of Tehran, Tehran, Iran
pp. 490-491

Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence (Abstract)

Zhaolin Li , Tsinghua University, P.R.China
Gongqiong Li , Tsinghua University, P.R.China
pp. 492-497

A comparison of low power architectures for digital delay measurement (Abstract)

Pablo Mandolesi , Universidad Nacional del Sur, Bahia Blanca, Argentina
Alfonso Chacon-Rodriguez , Instituto Tecnol?ogico de Costa Rica
Pedro Julian , Universidad Nacional del Sur, Bahia Blanca, Argentina
Franco Martin-Pirchio , Universidad Nacional del Sur, Bahia Blanca, Argentina
pp. 498-499

A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications (Abstract)

M. Khalilzadeh , Tarbiat Modarres University, Iran
A. Nabavi , Tarbiat Modarres University, Iran
pp. 506-507

DSPstone Benchmark of CoDeL?s Automated Clock Gating Platform (Abstract)

Nikitas Dimopoulos , University of Victoria, BC, Canada
Nainesh Agarwal , University of Victoria, BC, Canada
pp. 508-509

An External Memory Circuit Validation Algorithm for Large VLSI Layouts (Abstract)

Prosenjit Gupta , International Institute of Information Technology, Hyderabad, India
Yokesh Kumar , International Institute of Information Technology, Hyderabad, India
pp. 510-511

Modeling Subthreshold Leakage Current in General Transistor Networks (Abstract)

Chris H. Kim , University of Minnesota, Minneapolis, MN, USA
Renato P. Ribas , UFRGS, Porto Alegre, Brazil
Andre I. Reis , Nangate Inc., Menlo Park, CA, USA
Paulo F Butzen , UFRGS, Porto Alegre, Brazil
pp. 512-513

Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies (Abstract)

Ali Afzali-Kusha , University of Tehran, Tehran, Iran
Vahid Moalemi , University of Tehran, Tehran, Iran
pp. 514-515

Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures (Abstract)

S. Eachempati , Pennsylvania State University, UP, USA
Yehia Massoud , Rice University, Houston, Texas, USA
N. Vijaykrishnan , Pennsylvania State University, UP, USA
Arthur Nieuwoudt , Rice University, Houston, Texas, USA
pp. 516-517
Author Index

Author Index (PDF)

pp. 518
81 ms
(Ver )