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2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2006)
Karlsruhe Germany
Mar. 2, 2006 to Mar. 3, 2006
ISBN: 0-7695-2533-4
TABLE OF CONTENTS

Multiprocessor Systems-on-Chips (PDF)

W. Wolf , Princeton University, NJ
pp. 4

Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system (Abstract)

Z. Khan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
T. Arslan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
J.S. Thompson , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
A.T. Erdogan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
pp. 6 pp.

Adaptive porting of analog IPs with reusable conservative properties (Abstract)

T. Nojima , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
S. Nakatake , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
T. Fujimura , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
K. Okazaki , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
Y. Kajitani , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
pp. 6 pp.

Metal fix and power network repair for SOC (Abstract)

Q.K. Zhu , Matrix Semicond. Inc., Castro Valley, CA
pp. 5 pp.

Multi-SP: a representation with united rectangles for analog placement and routing (Abstract)

Ning Fu , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
S. Nakatake , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
pp. 6 pp.

Formulating the empirical strategies in module generation of analog MOS layout (Abstract)

Tan Yan , R&D Center of Semicond. Design, Kitakyushu Univ., Fukuoka
pp. 6 pp.

An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessors (Abstract)

O. Ozturk , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
pp. 6 pp.

High speed low swing dynamic circuits with multiple supply and threshold voltages (Abstract)

Zhiyu Liu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., USA
V. Kursun , Dept. of Electr. & Comput. Eng., Wisconsin Univ., USA
pp. 6 pp.

High performance service-time-stamp computation for WFQ IP packet scheduling (Abstract)

C. McKillen , Inst. of Electron., Commun. & Inf. Technol., Belfast
S. Sezer , Inst. of Electron., Commun. & Inf. Technol., Belfast
Xin Xang , Inst. of Electron., Commun. & Inf. Technol., Belfast
pp. 6 pp.

Synthesis of pipelined SRSL circuits (Abstract)

R. Oreifej , Dept. of Electr. & Comput. Eng., Central Florida Univ., Orlando, FL
A. Alsharqawi , Dept. of Electr. & Comput. Eng., Central Florida Univ., Orlando, FL
pp. 6 pp.

An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standard (Abstract)

R.B. Prudencio , Microelectron. Syst. Inst., Darmstadt Univ. of Technol.
L.S. Indrusiak , Microelectron. Syst. Inst., Darmstadt Univ. of Technol.
M. Glesner , Microelectron. Syst. Inst., Darmstadt Univ. of Technol.
pp. 5 pp.

Autonomous realization of Boeing/JPL sensor electronics based on reconfigurable system-on-chip technology (Abstract)

E.F. Stefatos , Sch. of Eng. & Electron., Edinburgh Univ.
T. Arslan , Sch. of Eng. & Electron., Edinburgh Univ.
pp. 6 pp.

Defect-aware design paradigm for reconfigurable architectures (Abstract)

R. Jain , Indian Inst. of Technol., Delhi
A. Mukherjee , Indian Inst. of Technol., Delhi
K. Paul , Indian Inst. of Technol., Delhi
pp. 6 pp.

New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits (Abstract)

M. Hiibner , Inst. fur Technik der Informationsverarbeitung, Karlsruhe Univ.
C. Schuck , Inst. fur Technik der Informationsverarbeitung, Karlsruhe Univ.
M. Kiihnle , Inst. fur Technik der Informationsverarbeitung, Karlsruhe Univ.
J. Becker , Inst. fur Technik der Informationsverarbeitung, Karlsruhe Univ.
pp. 6 pp.

A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm (Abstract)

V. Aken'Ova , Dept. of Electr. & Comput. Eng., British Columbia Univ.
R. Saleh , Dept. of Electr. & Comput. Eng., British Columbia Univ.
pp. 6 pp.

QUKU: a two-level reconfigurable architecture (Abstract)

S. Shukla , Queensland Univ., Brisbane, Qld.
pp. 6 pp.

Space-saving layout for passive components (Abstract)

P.H. Karjalainen , Inst. of Electron., Tampere Univ. of Technol., Finland
P. Heino , Inst. of Electron., Tampere Univ. of Technol., Finland
pp. 5 pp.

A novel low power multilevel current mode interconnect system (Abstract)

S. Joshi , Dept. of Electr. Eng., Indian Inst. of Technol., Bombay
D. Sharma , Dept. of Electr. Eng., Indian Inst. of Technol., Bombay
pp. 6 pp.

The design of analog front-end circuitry for 1x HD-DVD PRML read channel (Abstract)

Sheng-Jang Lin , Ind. Technol. Res. Inst., Hsin Chu
I-Shun Chen , Ind. Technol. Res. Inst., Hsin Chu
Bo-Wei Chen , Ind. Technol. Res. Inst., Hsin Chu
Feng-Hsiang Lo , Ind. Technol. Res. Inst., Hsin Chu
pp. 5 pp.

Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learning (Abstract)

M. Figueroa , Dept. of Electr. Eng., Univ. de Concepcion, Chile
E. Matamala , Dept. of Electr. Eng., Univ. de Concepcion, Chile
G. Carvajal , Dept. of Electr. Eng., Univ. de Concepcion, Chile
pp. 6 pp.

Verification of scheduling in high-level synthesis (Abstract)

C. Karfa , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India
C. Mandal , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India
D. Sarkar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India
S.R. Pentakota , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India
pp. 6 pp.

An efficient wrapper scan chain configuration method for network-on-chip testing (Abstract)

Ming Li , Dept. of Electr. & Comput. Eng. & Comput. Sci., Cincinnati Univ., OH
Wen-Ben Jone , Dept. of Electr. & Comput. Eng. & Comput. Sci., Cincinnati Univ., OH
Qing-An Zeng , Dept. of Electr. & Comput. Eng. & Comput. Sci., Cincinnati Univ., OH
pp. 6 pp.

An efficient data-independent technique for compressing test vectors in systems-on-a-chip (Abstract)

Xiaoyu Ruan , Dept. of Electr. & Comput. Eng., North Dakota State Univ., USA
Rajendra Katti , Dept. of Electr. & Comput. Eng., North Dakota State Univ., USA
pp. 6 pp.

Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs (Abstract)

K. Paulsson , Univ. Karlsruhe, Germany
M. Hubner , Univ. Karlsruhe, Germany
M. Jung , Univ. Karlsruhe, Germany
J. Becker , Univ. Karlsruhe, Germany
pp. 6 pp.

Design and analysis of a low power VLIW DSP core (Abstract)

Chan-Hao Chang , Ind. Technol. Res. Inst., Hsin Chu, Taiwan
pp. 6 pp.

High-performance noise-robust asynchronous circuits (Abstract)

P. Golani , Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA
P.A. Beerel , Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA
pp. 6 pp.

A low power lookup technique for multi-hashing network applications (Abstract)

I. Kaya , Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL
T. Kocak , Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL
pp. 6 pp.

A low power pipelined maximum likelihood detector for 4/spl times/4 QPSK MIMO wireless communication systems (Abstract)

J.H. Han , Sch. of Eng. & Electron., Edinburgh Univ.
A.T. Erdogan , Sch. of Eng. & Electron., Edinburgh Univ.
T. Arslan , Sch. of Eng. & Electron., Edinburgh Univ.
pp. 5 pp.

Optimal periodical memory allocation for logic-in-memory image processors (Abstract)

M. Hariyama , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai
M. Kameyama , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai
pp. 6 pp.

Globally asynchronous locally synchronous wrapper circuit based on clock gating (Abstract)

E. Amini , Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Iran
M. Najibi , Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Iran
H. Pedram , Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Iran
pp. 6 pp.

Connection-oriented multicasting in wormhole-switched networks on chip (Abstract)

Zhonghai Lu , Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm
Bei Yin , Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm
A. Jantsch , Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm
pp. 6 pp.

A virtual channel network-on-chip for GT and BE traffic (Abstract)

N. Kavaldjiev , Dept. of EEMCS, Twente Univ.
G.J.M. Smit , Dept. of EEMCS, Twente Univ.
P.G. Jansen , Dept. of EEMCS, Twente Univ.
P.T. Wolkotte , Dept. of EEMCS, Twente Univ.
pp. 6 pp.

Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling (Abstract)

E. Nigussie , Dept. of Inf. Technol., Turku Univ.
J. Plosila , Dept. of Inf. Technol., Turku Univ.
J. Isoaho , Dept. of Inf. Technol., Turku Univ.
pp. 6 pp.

Nanowire addressing in the face of uncertainty (Abstract)

E. Rachlin , Dept. of Comput. Sci., Brown Univ., USA
J.E. Savage , Dept. of Comput. Sci., Brown Univ., USA
pp. 6 pp.

Si nanocrystal MOSFET with silicon nitride tunnel insulator for high-rate random number generation (Abstract)

R. Ohba , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
D. Matsushita , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
K. Muraoka , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
S. Yasuda , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
T. Tanamoto , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
K. Uchida , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
S. Fujita , Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
pp. 6 pp.

Finite state machine implementation with single-electron tunneling technology (Abstract)

Jialin Mi , Dept. of Electr. & Comput. Eng., Windsor Univ., Ont.
Chunhong Chen , Dept. of Electr. & Comput. Eng., Windsor Univ., Ont.
pp. 5 pp.

PLAs in quantum-dot cellular automata (Abstract)

Xiaobo Sharon Hu , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN
M. Crocker , Dept. of Comp. Sci. & Eng., Notre Dame Univ., IN
pp. 6 pp.

Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration manager (Abstract)

P. Benoit , LIRMM, Montpellier Univ.
L. Torres , LIRMM, Montpellier Univ.
G. Sassatelli , LIRMM, Montpellier Univ.
M. Robert , LIRMM, Montpellier Univ.
G. Cambon , LIRMM, Montpellier Univ.
pp. 6 pp.

Regular routing architecture for a LUT-based MPGA (Abstract)

F.-J. Veredas , Infineon Technol. AG, Munich
M. Scheppler , Infineon Technol. AG, Munich
Bumei Zhai , Infineon Technol. AG, Munich
pp. 6 pp.

A new multilevel hierarchical MFPGA and its suitable configuration tools (Abstract)

Z. Marrakchi , Dept. ASIM-LIP6, Univ. Paris, France
H. Mrabet , Dept. ASIM-LIP6, Univ. Paris, France
H. Mehrez , Dept. ASIM-LIP6, Univ. Paris, France
pp. 6 pp.

New nonvolatile FPGA concept using magnetic tunneling junction (Abstract)

N. Bruchon , LIRMM, Montpellier
L. Torres , LIRMM, Montpellier
G. Sassatelli , LIRMM, Montpellier
G. Cambon , LIRMM, Montpellier
pp. 6 pp.

Profile directed instruction cache tuning for embedded systems (Abstract)

K. Vivekanandarajah , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
T. Srikanthan , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
pp. 6 pp.

Complexity and low power issues for on-chip interconnections in MPSoC system level design (Abstract)

Y. Sheynin , St. Petersburg State Univ. of Aerosp. Instrum., Russia
E. Suvorova , St. Petersburg State Univ. of Aerosp. Instrum., Russia
F. Shutenko , St. Petersburg State Univ. of Aerosp. Instrum., Russia
pp. 6 pp.

Fast configuration of an energy-efficient branch predictor (Abstract)

P. Hallschmid , Dept. of Electr. & Comput. Eng., British Columbia Univ.
R. Saleh , Dept. of Electr. & Comput. Eng., British Columbia Univ.
pp. 6 pp.

Exploiting software pipelining for network-on-chip architectures (Abstract)

Feihui Li , Dept. of CSE, Pennsylvania State Univ., University Park, PA
M. Kandemir , Dept. of CSE, Pennsylvania State Univ., University Park, PA
pp. 6 pp.

Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms (Abstract)

T. Schlichter , Dept. of Comput. Sci., Erlangen-Nuremberg Univ., Erlangen
M. Lukasiewycz , Dept. of Comput. Sci., Erlangen-Nuremberg Univ., Erlangen
C. Haubelt , Dept. of Comput. Sci., Erlangen-Nuremberg Univ., Erlangen
J. Teich , Dept. of Comput. Sci., Erlangen-Nuremberg Univ., Erlangen
pp. 6 pp.

Optimisation of the SHA-2 family of hash functions on FPGAs (Abstract)

R.P. McEvoy , Dept. of Electr. & Electron. Eng., Cork Univ. Coll.
F.M. Crowe , Dept. of Electr. & Electron. Eng., Cork Univ. Coll.
C.C. Murphy , Dept. of Electr. & Electron. Eng., Cork Univ. Coll.
W.P. Marnane , Dept. of Electr. & Electron. Eng., Cork Univ. Coll.
pp. 6 pp.

A novel approach to performance-oriented datapath allocation and floorplanning (Abstract)

V. Sundaresan , Dept. of ECECS, Cincinnati Univ., OH
R. Vemuri , Dept. of ECECS, Cincinnati Univ., OH
pp. 6 pp.

CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL (Abstract)

N. Ranganathan , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
R. Namballa , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
N. Hanchate , Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
pp. 6 pp.

System exploration of SystemC designs (Abstract)

C. Genz , Inst. of Comput. Sci., Bremen Univ., Germany
R. Drechsler , Inst. of Comput. Sci., Bremen Univ., Germany
pp. 6 pp.

Reliability-aware SOC voltage islands partition and floorplan (Abstract)

Shengqi Yang , Dept. of Electr. Eng., Princeton Univ., USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., USA
pp. 6 pp.

Ultra-low energy computing with noise: Energy performance probability (Abstract)

P. Korkmaz , Center for Res. on Embedded Syst. & Technol., Georgia Inst. of Technol., USA
B.E.S. Akgul , Center for Res. on Embedded Syst. & Technol., Georgia Inst. of Technol., USA
K.V. Palem , Center for Res. on Embedded Syst. & Technol., Georgia Inst. of Technol., USA
pp. 6 pp.

Power-oriented delay budgeting for combinational circuits (Abstract)

Jialin Mi , Dept. of Electr. & Comput. Eng., Windsor Univ., Windsor, Ont.
Chunhong Chen , Dept. of Electr. & Comput. Eng., Windsor Univ., Windsor, Ont.
pp. 4 pp.

Routing-tree construction with concurrent performance, power and congestion optimization (Abstract)

C. Alkan , Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO
T. Chen , Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO
pp. 6 pp.

Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology (Abstract)

A.S. Seyedi , Dept. of Elec. & Comp. Eng., Tehran Univ., Iran
S.H. Rasouli , Dept. of Elec. & Comp. Eng., Tehran Univ., Iran
A. Amirabadi , Dept. of Elec. & Comp. Eng., Tehran Univ., Iran
A. Afzali-Kusha , Dept. of Elec. & Comp. Eng., Tehran Univ., Iran
pp. 5 pp.

Performance and power analysis of globally asynchronous locally synchronous multiprocessor systems (Abstract)

Zhiyi Yu , Dept. of Electr. & Comput. Eng., California Univ., CA
B.M. Baas , Dept. of Electr. & Comput. Eng., California Univ., CA
pp. 6 pp.

Implementing register files for high-performance microprocessors in a die-stacked (3D) technology (Abstract)

K. Puttaswamy , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
pp. 6 pp.

Leakage-aware SPM management (Abstract)

Guangyu Chen , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA
Feihui Li , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA
O. Ozturk , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA
Guilin Chen , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA
M. Kandemir , Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA
pp. 6 pp.

Dependability analysis of nano-scale FinFET circuits (Abstract)

Feng Wang , Dept. of Comput. Sci. Eng., Pennsylvania State Univ., University Park, PA
Yuan Xie , Dept. of Comput. Sci. Eng., Pennsylvania State Univ., University Park, PA
pp. 6 pp.

A low-power 2D bypassing multiplier using 0.35 μm CMOS technology (Abstract)

Chua-Chin Wang , Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Taiwan
Gang-Neng Sung , Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Taiwan
pp. 4 pp.

Multi-level buffer block planning and buffer insertion for large design circuits (Abstract)

A. Jahanian , Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Tehran
pp. 5 pp.

Towards a faster simulation of SystemC designs (Abstract)

A. Habibi , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
H. Moinudeen , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
A. Samarah , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
S. Tahar , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
pp. 2 pp.

An optimized BIST architecture for FPGA look-up table testing (Abstract)

M.S. Yarandi , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
A. Alaghi , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Z. Navabi , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 2 pp.

Variation aware placement for FPGAs (Abstract)

S. Srinivasan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
V. Narayanan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
pp. 2 pp.

A regular layout approach for ASICs (Abstract)

C. Menezes , Instituto de Informatica, UFRGS, Brazil
C. Meinhard , Instituto de Informatica, UFRGS, Brazil
R. Reis , Instituto de Informatica, UFRGS, Brazil
pp. 2 pp.

Dual-mode high-speed low-energy binary addition (Abstract)

J. Grad , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
J.E. Stine , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
pp. 2 pp.

A flexible architecture for block turbo decoders using BCH or Reed-Solomon components codes (Abstract)

E. Piriou , CNRS TAMCIC UMR, Brest
C. Jego , CNRS TAMCIC UMR, Brest
P. Adde , CNRS TAMCIC UMR, Brest
M. Jezequel , CNRS TAMCIC UMR, Brest
pp. 2 pp.

Transparent management of reconfigurable hardware in embedded operating systems (Abstract)

K. Kociuszkiewicz , Dept. of Electron. Eng., Ireland Nat. Univ., Galway
F. Morgan , Dept. of Electron. Eng., Ireland Nat. Univ., Galway
K. Kepa , Dept. of Electron. Eng., Ireland Nat. Univ., Galway
pp. 2 pp.

An open-source tool for simulation of partially reconfigurable systems using SystemC (Abstract)

A.V. de Brito , Dept. de Engenharia Eletrica, Univ. Fed. de Campina Grande
E.U.K. Melcher , Dept. de Engenharia Eletrica, Univ. Fed. de Campina Grande
W. Rosas , Dept. de Engenharia Eletrica, Univ. Fed. de Campina Grande
pp. 2 pp.

Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation (Abstract)

F. Berthelot , CNRS UMR 6164, IETR-INSA, Rennes
F. Nouvel , CNRS UMR 6164, IETR-INSA, Rennes
pp. 2 pp.

Self-timed thermally-aware circuits (Abstract)

D. Fang , Comput. Syst. Lab., Cornell Univ., Ithaca, NY
F. Akopyan , Comput. Syst. Lab., Cornell Univ., Ithaca, NY
R. Manohar , Comput. Syst. Lab., Cornell Univ., Ithaca, NY
pp. 2 pp.

A new protocol stack model for network on chip (Abstract)

M. Dehyadgari , Sch. of Electr. & Comput. Eng., Tehran Univ.
M. Nickray , Sch. of Electr. & Comput. Eng., Tehran Univ.
A. Afzali-kusha , Sch. of Electr. & Comput. Eng., Tehran Univ.
Z. Navabi , Sch. of Electr. & Comput. Eng., Tehran Univ.
pp. 3 pp.

A robust synchronizer (Abstract)

Jun Zhou , Newcastle Univ.
D. Kinniment , Newcastle Univ.
G. Russell , Newcastle Univ.
A. Yakovlev , Newcastle Univ.
pp. 2 pp.

Low power layered space-time channel detector architecture for MIMO systems (Abstract)

T. Takahashi , Inst. for Syst. Level Integration, Livingston
A.T. Erdogan , Inst. for Syst. Level Integration, Livingston
T. Arslan , Inst. for Syst. Level Integration, Livingston
J.H. Han , Inst. for Syst. Level Integration, Livingston
pp. 2 pp.

Reducing memory requirements through task recomputation in embedded multi-CPU systems (Abstract)

H. Koc , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., USA
S. Tosun , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., USA
O. Ozturk , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., USA
M. Kandemir , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., USA
pp. 2 pp.

Compiler-directed management of leakage power in software-managed memories (Abstract)

G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
M. Li , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
O. Ozturk , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
pp. 2 pp.

A VLSI GFP frame delineation circuit (Abstract)

C. Toal , Inst. of Commun. & Inf. Technol., Queen Univ., Belfast, UK
S. Sezer , Inst. of Commun. & Inf. Technol., Queen Univ., Belfast, UK
Xin Yang , Inst. of Commun. & Inf. Technol., Queen Univ., Belfast, UK
pp. 2 pp.

Effects of parameter variations and crosstalk noise on H-tree clock distribution networks (Abstract)

I. Chanodia , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
D. Velenis , Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
pp. 2 pp.

Author index (PDF)

pp. 459
Poster Papers

Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation (Abstract)

Fabienne Nouvel , CNRS UMR 6164 IETR-INSA, Rennes, France
Florent Berthelot , CNRS UMR 6164 IETR-INSA, France
pp. 436-437

Self-Timed Thermally-Aware Circuits (Abstract)

Filipp Akopyan , Cornell University, NY
David Fang , Cornell University, NY
Rajit Manohar , Cornell University, NY
pp. 438-439

A New Protocol Stack Model for Network on Chip (Abstract)

Ali Afzali-kusha , University of Tehran, Iran
Masood Dehyadgari , University of Tehran, Iran
Zainalabedin Navabi , Northeastern University
Mohsen Nickray , University of Tehran, Iran
pp. 440-441

A Robust Synchronizer (Abstract)

Jun Zhou , Newcastle University, UK
David Kinniment , Newcastle University, UK
Alex Yakovlev , Newcastle University, UK
Gordon Russell , Newcastle University, UK
pp. 442-443

Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems (Abstract)

T. Takahashi , Institute for System Level Integration, Livingston, UK
T. Arslan , University of Edinburgh, UK
J. H. Han , University of Edinburgh, UK
A.T. Erdogan , University of Edinburgh, UK
pp. 444-445

Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems (Abstract)

Dietmar Scheiblhofer , Infineon Technologies, Austria AG
Josef Haid , Infineon Technologies, Austria AG
pp. 446-447

Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems (Abstract)

M. Kandemir , Pennsylvania State University
O. Ozturk , Pennsylvania State University
H. Koc , Syracuse University
S. Tosun , Syracuse University
pp. 448-449

Compiler-Directed Management of Leakage Power in Software-Managed Memories (Abstract)

M. Kandemir , Pennsylvania State University
O. Ozturk , Pennsylvania State University
F. Li , Pennsylvania State University
I. Demirkiran , Syracuse University, NY
G. Chen , Pennsylvania State University
pp. 450-451

A Parallel Architecture for Hardware Face Detection (Abstract)

T. Theocharides , University of Cyprus
M. J. Irwin , Penn State University
N. Vijaykrishnan , Penn State University
pp. 452-453

A VLSI GFP Frame Delineation Circuit (Abstract)

Ciaran Toal , Queen?s University Belfast, Northern
Sakir Sezer , Queen?s University Belfast, Northern
Xin Yang , Queen?s University Belfast, Northern
pp. 454-455

Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks (Abstract)

Itisha Chanodia , Illinois Institute of Technology, Chicago
Dimitrios Velenis , Illinois Institute of Technology, Chicago
pp. 456-457
Author Index

Author Index (PDF)

pp. 459
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