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2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2006)
Karlsruhe Germany
Mar. 2, 2006 to Mar. 3, 2006
ISBN: 0-7695-2533-4
TABLE OF CONTENTS

Multiprocessor Systems-on-Chips (PDF)

W. Wolf , Princeton University, NJ
pp. 4

Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system (Abstract)

Z. Khan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
T. Arslan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
J.S. Thompson , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
A.T. Erdogan , Syst. Level Integration Group Sch. of Eng. & Electron., Edinburgh Univ., UK
pp. 6 pp.

Adaptive porting of analog IPs with reusable conservative properties (Abstract)

T. Nojima , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
S. Nakatake , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
T. Fujimura , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
K. Okazaki , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
Y. Kajitani , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
pp. 6 pp.

Metal fix and power network repair for SOC (Abstract)

Q.K. Zhu , Matrix Semicond. Inc., Castro Valley, CA
pp. 5 pp.

Multi-SP: a representation with united rectangles for analog placement and routing (Abstract)

Ning Fu , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
S. Nakatake , Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
pp. 6 pp.

Formulating the empirical strategies in module generation of analog MOS layout (Abstract)

Tan Yan , R&D Center of Semicond. Design, Kitakyushu Univ., Fukuoka
pp. 6 pp.

An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessors (Abstract)

O. Ozturk , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
G. Chen , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
pp. 6 pp.

High speed low swing dynamic circuits with multiple supply and threshold voltages (Abstract)

Zhiyu Liu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., USA
V. Kursun , Dept. of Electr. & Comput. Eng., Wisconsin Univ., USA
pp. 6 pp.
Introduction
Keynotes

Multiprocessor Systems-on-Chips (PDF)

Wayne Wolf , Princeton University, NJ
pp. 4
Intellectual Property and Design

Floorplanning Based on Particle Swarm Optimization (Abstract)

Cheng-Wei Lin , National Dong Hwa University Hualien, Taiwan
Hsiang-Min Wang , National Dong Hwa University Hualien, Taiwan
Sheng-Ta Hsieh , National Dong Hwa University Hualien, Taiwan
Tsung-Ying Sun , National Dong Hwa University Hualien, Taiwan
pp. 7-11

Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System (Abstract)

Tughrul Arslan , Institute of System Level Integration, ALBA Campus, UK
Ahmet T. Erdogan , Institute of System Level Integration, ALBA Campus, UK
John S. Thompson , University of Edinburgh, UK
Zahid Khan , University of Edinburgh,UK
pp. 12-17

Adaptive Porting of Analog IPs with Reusable Conservative Properties (Abstract)

Shigetoshi Nakatake , University of Kitakyushu, Japan
Toru Fujimura , University of Kitakyushu, Japan
Takashi Nojima , Jedat Innovation Inc., Japan
Koji Okazaki , University of Kitakyushu, Japan
Nobuto Ono , Jedat Innovation Inc., Japan
Yoji Kajitani , University of Kitakyushu, Japan
pp. 18-23

VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography (Abstract)

Rolf Ernst , Technical University of Braunschweig, Braunschweig, Germany
Abdulrahman Hanoun , Technical University Hamburg, Harburg, Germany
Wael Adi , Technical University of Braunschweig, Braunschweig, Germany
Bassel Soudan , University of Sharjah, Sharjah, United Arab Emirate
pp. 24-32
Physical Design

Metal Fix and Power Network Repair for SOC (Abstract)

Paige Kolze , Xilinx Inc., San Jose, CA
Qing K. Zhu , Matrix Semiconductor Inc.
pp. 33-37

Multi-SP: A Representation with United Rectangles for Analog Placement and Routing (Abstract)

Ning Fu , Jedat Innovation Inc., Japan
Shigetoshi Nakatake , University of Kitakyushu, Japan
Mitsutoshi Mineshima , Jedat Innovation Inc., Japan
pp. 38-43

Formulating the Empirical Strategies in Module Generation of Analog MOS Layout (Abstract)

Takashi Nojima , University of Kitakyushu, Japan
Shigetoshi Nakatake , University of Kitakyushu, Japan
Tan Yan , R&D Center of Semiconductor Design, Japan
pp. 44-49

An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors (Abstract)

M. Kandemir , Pennsylvania State University
M. Karakoy , Imperial College London, UK
G. Chen , Pennsylvania State University
O. Ozturk , Pennsylvania State University
pp. 50-58
High Performance Circuits

High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages (Abstract)

Volkan Kursun , University of Wisconsin, Madison
Zhiyu Liu , University of Wisconsin, Madison
pp. 59-64

High performance service-time-stamp computation for WFQ IP packet scheduling (Abstract)

C. McKillen , Institute of Electronics, Communications and Information Technology
Xin Yang , Institute of Electronics, Communications and Information Technology
S. Sezer , Institute of Electronics, Communications and Information Technology
pp. 65-70

Synthesis of Pipelined SRSL Circuits (Abstract)

Abdel Ejnioui , University of South Florida
Rashad Oreifej , University of Central Florida
Abdelhalim Alsharqawi , University of Central Florida
pp. 71-76

An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard (Abstract)

Leandro Soares Indrusiak , Microelectronic Systems Institute, Darmstadt, Germany
Romualdo Begale Prudencio , Microelectronic Systems Institute, Darmstadt, Germany
Manfred Glesner , Darmstadt University of Technology, Darmstadt, Germany
pp. 77-84

Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs (Abstract)

K. Paulsson , Univ. Karlsruhe, Germany
M. Hubner , Univ. Karlsruhe, Germany
M. Jung , Univ. Karlsruhe, Germany
J. Becker , Univ. Karlsruhe, Germany
pp. 6 pp.
Reconfigurable Systems Integration

Defect-Aware Design Paradigm for Reconfigurable Architectures (Abstract)

Anindita Mukherjee , Indian Institute of Technology, Delhi
Rahul Jain , Indian Institute of Technology, Delhi
Kolin Paul , Indian Institute of Technology, Delhi
pp. 91-96

New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits (Abstract)

Christian Schuck , Universit?t Karlsruhe (TH), Germany
Matthias Kuhnle , Universitat Karlsruhe (TH), Germany
Jurgen Becker , Universitat Karlsruhe (TH), Germany
Michael Hubner , Universit?t Karlsruhe (TH), Germany
pp. 97-102

A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm (Abstract)

Resve Saleh , University of British Columbia
Victor Aken Ova , University of British Columbia
pp. 103-108

QUKU: A Two-Level Reconfigurable Architecture (Abstract)

Sunil Shukla , ITEE, University of Queensland, Australia,
Neil W. Bergmann , ITEE, University of Queensland, Australia,
Jurgen Becker , ITIV, Universit?t Karlsruhe, Germany
pp. 109-116
Mixed-Signal Design and Analysis

Space-Saving Layout for Passive Components (Abstract)

Pekka Heino , Tampere University of Technology, Institute of Electronics
Paivi H. Karjalainen , Tampere University of Technology, Institute of Electronics
pp. 117-121

A Novel Low Power Multilevel Current Mode Interconnect System (Abstract)

Dinesh Sharma , Indian Institute of Technology, Bombay, India
Supreet Joshi , Indian Institute of Technology, Bombay, India
pp. 122-127

The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel (Abstract)

Feng-Hsiang Lo , Industrial Technology Research Institute, Taiwan
I-Shun Chen , Industrial Technology Research Institute, Taiwan
Sheng-Jang Lin , Industrial Technology Research Institute, Taiwan
Bo-Wei Chen , Industrial Technology Research Institute, Taiwan
pp. 128-132

Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning (Abstract)

Esteban Matamala , Universidad de Concepcion Concepcion, Chile
Miguel Figueroa , Universidad de Concepcion Concepcion, Chile
Gonzalo Carvajal , Universidad de Concepcion Concepcion, Chile
Seth Bridges , University of Washington Seattle, WA
pp. 133-140
Test and Verification

Verification of Scheduling in High-level Synthesis (Abstract)

C Mandal , Indian Institute of Technology, Kharagpur
C Karfa , Indian Institute of Technology, Kharagpur
Chris Reade , Kingston Universitym, UK
D Sarkar , Indian Institute of Technology, Kharagpur
S R Pentakota , Indian Institute of Technology, Kharagpur
pp. 141-146

An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing (Abstract)

Ming Li , University of Cincinnati, Cincinnati OH
Wen-Ben Jone , University of Cincinnati, Cincinnati OH
Qing-An Zeng , University of Cincinnati, Cincinnati OH
pp. 147-152

An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip (Abstract)

Rajendra Katti , North Dakota State University, Fargo, ND
Xiaoyu Ruan , North Dakota State University, Fargo, ND
pp. 153-158

Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs (Abstract)

Markus Jung , Universitaet Karlsruhe (TH), Germany
J?rgen Becker , Universitaet Karlsruhe (TH), Germany
Michael Hubner , Universitaet Karlsruhe (TH), Germany
Katarina Paulsson , Universitaet Karlsruhe (TH), Germany
pp. 159-166
Low Power System Design

Design and Analysis of a Low Power VLIW DSP Core (Abstract)

Chan-Hao Chang , Industrial Technology Research Institute
Diana Marculescu , Carnegie Mellon University
pp. 167-172

High-Performance Noise-Robust Asynchronous Circuits (Abstract)

Pankaj Golani , University of Southern California, Los Angeles
Peter A. Beerel , University of Southern California, Los Angeles
pp. 173-178

A Low Power Lookup Technique for Multi-Hashing Network Applications (Abstract)

Taskin Kocak , University of Central Florida
Ilhan Kaya , University of Central Florida
pp. 179-184

A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems (Abstract)

T. Arslan , Institute of System Level Integration, Alba Campus, UK
J.H Han , University of Edinburgh, UK
A.T Erdogan , Institute of System Level Integration, Alba Campus, UK
pp. 185-192
System-on-Chip

Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors (Abstract)

Michitaka Kameyama , Tohoku University, Japan
Yasuhiro Kobayashi , Oyama National College of Technology, Japan
Masanori Hariyama , Tohoku University, Japan
pp. 193-198

Profile directed instruction cache tuning for embedded systems (Abstract)

K. Vivekanandarajah , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
T. Srikanthan , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
pp. 6 pp.
System-on-Chip

Connection-oriented Multicasting in Wormhole-switched Networks on Chip (Abstract)

Axel Jantsch , Royal Institute of Technology, Sweden
Zhonghai Lu , Royal Institute of Technology, Sweden
Bei Yin , Royal Institute of Technology, Sweden
pp. 205-2110

A Virtual Channel Network-on-Chip for GT and BE traffic (Abstract)

Pascal T. Wolkotte , University of Twente, the Netherlands
Pierre G. Jansen , University of Twente, the Netherlands
Nikolay Kavaldjiev , University of Twente, the Netherlands
Gerard J. M. Smit , University of Twente, the Netherlands
pp. 211-216

Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling (Abstract)

Juha x , , University of Turku, Finland
Ethiopia Nigussie , University of Turku, Finland
Jouni Isoaho , University of Turku, Finland
pp. 217-224
Nano Electronics

Nanowire Addressing in the Face of Uncertainty (Abstract)

Eric Rachlin , Brown University
John E. Savage , Brown University
pp. 225-230

Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation (Abstract)

Shinichi Yasuda , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Shinobu Fujita , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Daisuke Matsushita , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Ryuji Ohba , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Koichi Muraoka , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Ken Uchida , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
Tetsufumi Tanamoto , Advanced LSI Technology Laboratory, Toshiba Corporation, Japan
pp. 231-236

Finite State Machine Implementation with Single-Electron Tunneling Technology (Abstract)

Chunhong Chen , University of Windsor, Ontario, Canada
Jialin Mi , University of Windsor, Ontario, Canada
pp. 237-241

PLAs in Quantum-dot Cellular Automata (Abstract)

Michael Niemier , Georgia Institute of Technology, Atlanta
Gary Bernstein , University of Notre Dame
Minjun Yan , University of Notre Dame
Michael Crocker , University of Notre Dame
Xiaobo Sharon Hu , University of Notre Dame
pp. 242-250
Reconfigurable System Design and Technologies

Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager (Abstract)

G. Sassatelli , LIRMM, UMR University of Montpellier 2-CNRS, France
J. Becker , University of Karlsruhe
M. Robert , LIRMM, UMR University of Montpellier 2-CNRS, France
G. Cambon , LIRMM, UMR University of Montpellier 2-CNRS, France
P. Benoit , LIRMM, UMR University of Montpellier 2-CNRS, France
L. Torres , LIRMM, UMR University of Montpellier 2-CNRS, France
pp. 251-256

Regular Routing Architecture for a LUT-based MPGA (Abstract)

Bumei Zhai , University of Ulm, Ulm, Germany
Michael Scheppler , Infineon Technologies AG ,Munich, Germany
Hans-Joerg Pfleiderer , University of Ulm, Ulm, Germany
Francisco-Javier Veredas , Infineon Technologies AG ,Munich, Germany
pp. 257-262

A new Multilevel Hierarchical MFPGA and its suitable configuration tools (Abstract)

Zied Marrakchi , Universit e Paris 6, Pierre et Marie Curie
Hayder Mrabet , Universite Paris 6, Pierre et Marie Curie
Habib Mehrez , Universite Paris 6, Pierre et Marie Curie
pp. 263-268

New non-volatile FPGA concept using Magnetic Tunneling Junction (Abstract)

Gaston Cambon , LIRMM, Cedex, France
Nicolas Bruchon , LIRMM, Cedex, France
Lionel Torres , LIRMM, Cedex, France
Gilles Sassatelli , LIRMM, Cedex, France
pp. 269-276
Complexity and System Organization

Profile Directed Instruction Cache Tuning for Embedded Systems (Abstract)

Kugan Vivekanandarajah , Nanyang Technological University Singapore
Christopher T. Clarke , University of Bath, UK
Thambipillai Srikanthan , Nanyang Technological University Singapore
pp. 277-282

Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design (Abstract)

Felix Shutenko , University of Aerospace Instrumentation, St. Petersburg, Russia
Elena Suvorova , University of Aerospace Instrumentation, St. Petersburg, Russia
Yuriy Sheynin , University of Aerospace Instrumentation, St. Petersburg, Russia
pp. 283-288

Fast Configuration of an Energy-Efficient Branch Predictor (Abstract)

R. Saleh , University of British Columbia, Vancouver
P. Hallschmid , University of British Columbia, Vancouver
pp. 289-294

Exploiting Software Pipelining for Network-on-Chip architectures (Abstract)

Mahmut Kandemir , Pennsylvania State University
Feihui Li , Pennsylvania State University
Ibrahim Kolcu , Computation Dept., UMIST, Manchester, UK
pp. 295-302
System Level and Circuit Analysis

An Efficient Algorithm for the Analysis of Cyclic Circuits (Abstract)

Stephen A. Edwards , Columbia University
Osama Neiroukh , Intel Corporation
Xiaoyu Song , Portland State University
pp. 303-308

Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms (Abstract)

Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany
Christian Haubelt , University of Erlangen-Nuremberg, Germany
Jurgen Teich , University of Erlangen-Nuremberg, Germany
Thomas Schlichter , University of Erlangen-Nuremberg, Germany
pp. 309-316
System Level Design

Optimisation of the SHA-2 Family of Hash Functions on FPGAs (Abstract)

Robert P. McEvoy , University College Cork, Ireland
Francis M. Crowe , University College Cork, Ireland
Colin C. Murphy , University College Cork, Ireland
William P. Marnane , University College Cork, Ireland
pp. 317-322

A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning (Abstract)

Ranga Vemuri , University of Cincinnati, OH
Vijay Sundaresan , University of Cincinnati, OH
pp. 323-328

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL (Abstract)

Narender Hanchate , University of South Florida, Tampa
Ravi Namballa , University of South Florida, Tampa
Nagarajan Ranganathan , University of South Florida, Tampa
pp. 329-334

System Exploration of SystemC Designs (Abstract)

Rolf Drechsler , University of Bremen, Germany
Christian Genz , University of Bremen, Germany
pp. 335-342
Power Aware VLSI Design

Reliability-Aware SOC Voltage Islands Partition and Floorplan (Abstract)

N. Vijaykrishnan , Penn State University
Shengqi Yang , Princeton University, Princeton, NJ
Yuan Xie , Penn State University
Wayne Wolf , Princeton University, Princeton, NJ
pp. 343-348

Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs (Abstract)

Pinar Korkrnaz , Georgia Institute of Technology, Atlanta
Krishna V. Palem , Georgia Institute of Technology, Atlanta
Bilge E. S. Akgul , Georgia Institute of Technology, Atlanta
pp. 349-354

Delay and Energy Efficient Data Transmission for On-Chip Buses (Abstract)

Yuan Xie , Pennsylvania State University
Madhu Mutyam , International Institute of Information Technology, Hyderabad, India
N. Vijaykrishnan , Pennsylvania State University
Melvin Eze , Pennsylvania State University
pp. 355-360

Power-Oriented Delay Budgeting for Combinational Circuits (Abstract)

Jialin Mi , University of Windsor, Ontario, Canada
Chunhong Chen , University of Windsor, Ontario, Canada
pp. 361-366
VLSI Circuits and Optimization

Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization (Abstract)

Cengiz Alkan , Colorado State University, Fort Collins
Tom Chen , Colorado State University, Fort Collins
pp. 367-372

Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology (Abstract)

S. H. Rasouli , University of Tehran, Iran
A. Afzali-Kusha , University of Tehran, Iran
A. S. Seyedi , University of Tehran, Iran
A. Amirabadi , University of Tehran, Iran
pp. 373-377

Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems (Abstract)

Bevan M. Baas , University of California, Davis
Zhiyi Yu , University of California, Davis
pp. 378-383

Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology (Abstract)

Gabriel H. Loh , Georgia Institute of Technology, Atlanta
Kiran Puttaswamy , Georgia Institute of Technology, Atlanta
pp. 384-392
VLSI Circuits and Technologies

Leakage-Aware SPM Management (Abstract)

Ozcan Ozturk , Pennsylvania State University
Guilin Chen , Pennsylvania State University
Feihui Li , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
Ibrahim Kolcu , UMIST, UK
Guangyu Chen , Pennsylvania State University
pp. 393-398

Dependability Analysis of Nano-scale FinFET circuits (Abstract)

Yuan Xie , Pennsylvania State University
Kerry Bernstein , IBM T.J. Watson Research Center, Yorktown Heights, NY
Yan Luo , Silicon Engineering Group, Synopsys .Inc, Shanghai, China
Feng Wang , Pennsylvania State University
pp. 399-404

A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology (Abstract)

Gang-Neng Sung , National Sun Yat-Sen University, Kaohsiung, Taiwan
Chua-Chin Wang , National Sun Yat-Sen University, Kaohsiung, Taiwan
pp. 405-410
Poster Papers

Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits (Abstract)

Ali Jahanian , Amirkabir University of Technology, Tehran, IRAN
Morteza Saheb Zamani , Amirkabir University of Technology, Tehran, IRAN
pp. 411-415

Towards a Faster Simulation of SystemC Designs (Abstract)

Sofiene Tahar , Concordia University
Amer Samarah , Concordia University
Haja Moinudeen , Concordia University
Ali Habibi , Concordia University
pp. 418-419

An Optimized BIST Architecture for FPGA Look-Up Table Testing (Abstract)

Zainalabedin Navabi , University of Tehran, Tehran, Iran
Mahnaz Sadoughi Yarandi , University of Tehran, Tehran, Iran
Armin Alaghi , University of Tehran, Tehran, Iran
pp. 420-421

Variation Aware Placement for FPGAs (Abstract)

Vijaykrishnan Narayanan , Pennsylvania State University
Suresh Srinivasan , Pennsylvania State University
pp. 422-423

A Regular Layout Approach for ASICs (Abstract)

Cristina Meinhardt , Instituto de Inform?tica -UFRGS, Brazil
Claudio Menezes , Instituto de Inform?tica -UFRGS, Brazil
Ricardo Reis , Instituto de Inform?tica -UFRGS, Brazil
Reginaldo Tavares , Universidade Estadual do Rio Grande do Sul
pp. 424-425

Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip (Abstract)

Leandro Soares Indrusiak , MES - TU Darmstadt, Germany
Jose C. S. Palma , PPGC - II - UFRGS, Brazil
Manfred Glesner , MES - TU Darmstadt, Germany
Ricardo A. L. Reis , PPGC - II - UFRGS, Brazil
Alberto Garcia Ortiz , MES - TU Darmstadt, Germany
Fernando G. Moraes , PPGCC - FACIN - PUCRS, Brazil
pp. 426-427

Dual-Mode High-Speed Low-Energy Binary Addition (Abstract)

Johannes Grad , Illinois Institute of Technology, Chicago
James E. Stine , Oklahoma State University
pp. 428-429

A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes (Abstract)

Michel JEZEQUEL , GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Erwan PIRIOU , GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Christophe JEGO , GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Patrick ADDE , GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
pp. 430-431

Transparent Management of Reconfigurable Hardware in Embedded Operating Systems (Abstract)

Krzysztof Kepa , Wrocaw University of Technology, Poland
Fearghal Morgan , Wrocaw University of Technology, Poland
Krzysztof Kosciuszkiewicz , National University of Ireland, Galway
pp. 432-433

An open-source tool for simulation of partially reconfigurable systems using SystemC (Abstract)

Wilson Rosas , Universidade Federal de Campina Grande - UFCG, Brazil
Elamr U. K. Melcher , Universidade Federal de Campina Grande - UFCG, Brazil
Alisson V. De Brito , Universidade Federal de Campina Grande - UFCG, Brazil
pp. 434-435

Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation (Abstract)

Fabienne Nouvel , CNRS UMR 6164 IETR-INSA, Rennes, France
Florent Berthelot , CNRS UMR 6164 IETR-INSA, France
pp. 436-437

Self-Timed Thermally-Aware Circuits (Abstract)

Filipp Akopyan , Cornell University, NY
David Fang , Cornell University, NY
Rajit Manohar , Cornell University, NY
pp. 438-439

A New Protocol Stack Model for Network on Chip (Abstract)

Ali Afzali-kusha , University of Tehran, Iran
Masood Dehyadgari , University of Tehran, Iran
Zainalabedin Navabi , Northeastern University
Mohsen Nickray , University of Tehran, Iran
pp. 440-441

A Robust Synchronizer (Abstract)

Jun Zhou , Newcastle University, UK
David Kinniment , Newcastle University, UK
Alex Yakovlev , Newcastle University, UK
Gordon Russell , Newcastle University, UK
pp. 442-443

Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems (Abstract)

T. Takahashi , Institute for System Level Integration, Livingston, UK
T. Arslan , University of Edinburgh, UK
J. H. Han , University of Edinburgh, UK
A.T. Erdogan , University of Edinburgh, UK
pp. 444-445

Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems (Abstract)

Dietmar Scheiblhofer , Infineon Technologies, Austria AG
Josef Haid , Infineon Technologies, Austria AG
pp. 446-447

Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems (Abstract)

M. Kandemir , Pennsylvania State University
O. Ozturk , Pennsylvania State University
H. Koc , Syracuse University
S. Tosun , Syracuse University
pp. 448-449

Compiler-Directed Management of Leakage Power in Software-Managed Memories (Abstract)

M. Kandemir , Pennsylvania State University
O. Ozturk , Pennsylvania State University
F. Li , Pennsylvania State University
I. Demirkiran , Syracuse University, NY
G. Chen , Pennsylvania State University
pp. 450-451

A Parallel Architecture for Hardware Face Detection (Abstract)

T. Theocharides , University of Cyprus
M. J. Irwin , Penn State University
N. Vijaykrishnan , Penn State University
pp. 452-453

A VLSI GFP Frame Delineation Circuit (Abstract)

Ciaran Toal , Queen?s University Belfast, Northern
Sakir Sezer , Queen?s University Belfast, Northern
Xin Yang , Queen?s University Belfast, Northern
pp. 454-455

Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks (Abstract)

Itisha Chanodia , Illinois Institute of Technology, Chicago
Dimitrios Velenis , Illinois Institute of Technology, Chicago
pp. 456-457
Author Index

Author Index (PDF)

pp. 459
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