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2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2005)
Tampa, Florida
May 11, 2005 to May 12, 2005
ISBN: 0-7695-2365-X
TABLE OF CONTENTS
Introduction

Symposium Committees (PDF)

pp. xi-xii
Emerging Trends in VLSI

Let?s Think Analog (Abstract)

Melvin A. Breuer , University of Southern California
pp. 2-5

Analysis of a Mask-Based Nanowire Decoder (Abstract)

Benjamin Gojman , Brown University
Eric Rachlin , Brown University
John E. Savage , Brown University
pp. 6-13

Bi-Direction Synthesis for Reversible Circuits (Abstract)

Guowu Yang , Portland State University
William N. N. Hung , Portland State University
Marek A. Perkowski , Portland State University
Xiaoyu Song , Portland State University
pp. 14-19
Advanced VLSI Design

Boost Logic: A High Speed Energy Recovery Circuit Family (Abstract)

Marios C. Papaefthymiou , University of Michigan
Conrad H. Ziesler , MultiGig Inc.
Visvesh S. Sathe , University of Michigan
pp. 22-27

High Performance Array Processor for Video Decoding (Abstract)

J. Lee , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
pp. 28-33

High Speed Redundant Adder and Divider in Output Prediction Logic (Abstract)

Xinyu Guo , University of Washington
Carl Sechen , University of Washington
pp. 34-41

Sensing Design Issues in Deep Submicron CMOS SRAMs (Abstract)

Atul Maheshwari , University of Massachusetts at Amherst
Aiyappan Natarajan , University of Massachusetts at Amherst
Vijay Shankar , University of Massachusetts at Amherst
Wayne Burleson , University of Massachusetts at Amherst
pp. 42-45
VLSI Circuits and Systems

409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS (Abstract)

Sheng Sun , University of Washington
Larry McMurchie , University of Washington
Yi Han , University of Washington
Kian Haur Chong , University of Washington
Xinyu Guo , University of Washington
Carl Sechen , University of Washington
pp. 52-58

Quasi-Exact BDD Minimization Using Relaxed Best-First Search (Abstract)

Rolf Drechsler , University of Bremen
Rüdiger Ebendt , University of Bremen
pp. 59-64
VLSI Circuits and Systems

Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams (Abstract)

Anuradha Agarwal , University of Cincinnati
Ranga Vemuri , University of Cincinnati
Huiying Yang , University of Cincinnati
pp. 71-76

A Modified Cascaded Sigma-Delta Modulator with Improved Linearity (Abstract)

Mohammed Ismail , LECS/ICT/Royal Institute of Technology Stockholm and Ohio State University
Hannu Tenhunen , LECS/ICT/Royal Institute of Technology Stockholm
Ana Rusu , LECS/ICT/Royal Institute of Technology Stockholm and Technical University of Cluj-Napoca
pp. 77-82
System-on-a-Chip Design

Jitter in Deep Sub-Micron Interconnect (Abstract)

Sheng Xu , University of Massachusetts
Jinwook Jang , University of Massachusetts
Wayne Burleson , University of Massachusetts
pp. 84-89

Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs (Abstract)

Mahmut Kandemir , Pennsylvania State University
Guilin Chen , Pennsylvania State University
Guangyu Chen , Pennsylvania State University
Ozcan Ozturk , Pennsylvania State University
pp. 90-95
System Level Design

eWatch: Context Sensitive System Design Case Study (Abstract)

Anthony Rowe , Carnegie Mellon University
Asim Smailagic , Carnegie Mellon University
Karen P. Tang , Carnegie Mellon University
Uwe Maurer , Carnegie Mellon University
Daniel P. Siewiorek , Carnegie Mellon University
pp. 98-103

A Data-Driven Approach for Embedded Security (Abstract)

R. Brooks , Pennsylvania State University
O. Ozturk , Pennsylvania State University
H. Saputra , Pennsylvania State University
M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
pp. 104-109

System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures (Abstract)

Vijaykumar Ramamurthi , Arizona State University
Jason McCollum , Arizona State University
Karam S. Chatha , Arizona State University
Christopher Ostler , Arizona State University
pp. 110-116
Field-Programmable and Reconfigurable Systems

A High Speed Reconfigurable Gate Array for Gigahertz Applications (Abstract)

Michael Chu , Rensselaer Polytechnic Institute
Chao You , Rensselaer Polytechnic Institute
Russell P. Kraft , Rensselaer Polytechnic Institute
John F. McDonald , Rensselaer Polytechnic Institute
Jong-Ru Guo , Rensselaer Polytechnic Institute
Okan Erdogan , Rensselaer Polytechnic Institute
pp. 124-129

Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k (Abstract)

M. A. Thornton , Southern Methodist University
L. Li , Southern Methodist University
Alex Fit-Florea , Southern Methodist University
D. W. Matula , Southern Methodist University
pp. 130-135

An Improved Dynamic Optically Reconfigurable Gate Array (Abstract)

Fuminori Kobayashi , Kyushu Institute of Technology
Minoru Watanabe , Kyushu Institute of Technology
pp. 136-141

Lemma Exchange in a Microcontroller Based Parallel SAT Solver (Abstract)

Tobias Schubert , Albert-Ludwigs-University of Freiburg
Bernd Becker , Albert-Ludwigs-University of Freiburg
pp. 142-147
Application-Specific Low Power VLSI System Design

Power Analysis of Rotary Clock (Abstract)

Zhengtao Yu , North Carolina State University
Xun Liu , North Carolina State University
pp. 150-155

On Reducing Peak Current and Power during Test (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
Wei Li , University of Iowa
pp. 156-161

Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic (Abstract)

Magdy Bayoumi , University of Louisiana at Lafayette
Soujanya Venigalla , University of Louisiana at Lafayette
Soumik Ghosh , University of Louisiana at Lafayette
pp. 162-166

Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths (Abstract)

Ranganath Gopalan , University of South Florida
Srinivas Katkoori , University of South Florida
Chandramouli Gopalakrishnan , University of South Florida
pp. 167-172

High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization (Abstract)

A. T. Erdogan , University of Edinburgh and Institute of System Level Integration
J. H. Han , University of Edinburgh
T. Arslan , University of Edinburgh and Institute of System Level Integration
pp. 173-178
Power Awareness in VLSI Design

Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters (Abstract)

Yuan Xie , Pennsylvania State University
Daniel Hostetler , Pennsylvania State University
pp. 186-191
Test and Verification

Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume (Abstract)

Il-Soo Lee , University of Texas at Austin
Jae Hoon Jeong , University of Texas at Austin
Anthony P. Ambler , University of Texas at Austin
pp. 194-199

Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier (Abstract)

Terence Rodrigues , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
Avijit Dutta , University of Texas at Austin
pp. 200-205

Fault Diagnosis and Fault Model Aliasing (Abstract)

Irith Pomeranz , Purdue University
Srikanth Venkataraman , Intel Corporation
Sudhakar M. Reddy , University of Iowa
pp. 206-211

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits (Abstract)

Junhao Shi , University of Bremen and Philips Semiconductors GmbH
Friedrich Hapke , University of Bremen and Philips Semiconductors GmbH
Rolf Drechsler , University of Bremen and Philips Semiconductors GmbH
J? Schl?ffel , University of Bremen and Philips Semiconductors GmbH
G?rschwin Fey , University of Bremen and Philips Semiconductors GmbH
Andreas Glowatz , University of Bremen and Philips Semiconductors GmbH
pp. 212-217

Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators (Abstract)

Hao Zheng , University of South Florida
Tian Xia , University of Vermont
Jing Li , IBM Microelectronics Division
Ahmed Ginawi , IBM Microelectronics Division
pp. 218-223
Physical Design

IR Drop and Ground Bounce Awareness Timing Model (Abstract)

Martin D. F. Wong , University of Illinois at Urbana-Champaign
Li-Pen Yuan , Synopsys Inc.
Muzhou Shao , Synopsys Inc.
Youxin Gao , Synopsys Inc.
pp. 226-231

Post-Placement Pin Optimiztion (Abstract)

Jurjen Westra , Eindhoven University of Technology
Patrick Groeneveld , Eindhoven University of Technology
pp. 238-243
Poster Papers

A Low Power Embedded Dataflow Coprocessor (PDF)

Steve Furber , University of Manchester
Yijun Liu , University of Manchester
pp. 246-247

Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits (PDF)

Hao Li , University of South Florida
R. Velagapudi , University of North Texas
Saraju P. Mohanty , University of North Texas
V. Mukherjee , University of North Texas
pp. 248-249

Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs (PDF)

Ranga Vemuri , University of Cincinnati
Renqiu Huang , University of Cincinnati
pp. 250-251

Reduction of Power and Test Time by Removing Cluster of Don?t-Care from Test Data Set (PDF)

Yu-Ting Lin , University of Texas at Austin
Anthony P. Ambler , University of Texas at Austin
Il-Soo Lee , University of Texas at Austin
pp. 255-256

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models (Abstract)

S. Pontarelli , University of Rome
L. Schiano , Northeastern University Boston
G. C. Cardarilli , University of Rome
M. Ottavi , Northeastern University Boston
F. Lombardi , Northeastern University Boston
pp. 257-259

Synthesis of Self-Resetting Stage Logic Pipelines (Abstract)

Abdelhalim Alsharqawi , University of Central Florida
Abdel Ejnioui , University of Central Florida
pp. 260-262

RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis (PDF)

Kaiping Zeng , Darmstadt University of Technology
Sorin A. Huss , Darmstadt University of Technology
pp. 266-267

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses (PDF)

Bertrand Le Gal , University of South Brittany
Eric Martin , University of South Brittany
Emmanuel Casseau , University of South Brittany
Sylvain Huet , University of South Brittany
pp. 268-269

The Use of Pre-Evaluation Phase in Dynamic CMOS Logic (PDF)

Y. Tsiatouhas , University of Ioannina
H. Djemil , Southern Illinois University
A. Rao , Southern Illinois University
Th. Haniotakis , Southern Illinois University
pp. 270-271

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding (PDF)

Jose L. Nunez-Yanez , University of Bristol
T. R. Jacobs , Loughborough University
V. A. Chouliaras , Loughborough University
Ashwin K. Kumaraswamy , Loughborough University
pp. 272-273

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs (PDF)

Minoru Watanabe , Kyushu Institute of Technology
Mototsugu Miyano , Kyushu Institute of Technology
Fuminori Kobayashi , Kyushu Institute of Technology
pp. 274-275

Wire Length Distribution Model Considering Core Utilization for System on Chip (PDF)

Hidenari Nakashima , Tokyo Institute of Technology
Junpei Inoue , Tokyo Institute of Technology
Takumi Uezono , Tokyo Institute of Technology
Takanori Kyogoku , Tokyo Institute of Technology
Kazuya Masu , Tokyo Institute of Technology
Kenichi Okada , Tokyo Institute of Technology
pp. 276-277

12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes (PDF)

John F McDonald , Rensselaer Polytechnic Institute
Russell P. Kraft , Rensselaer Polytechnic Institute
Young Uk Yim , Rensselaer Polytechnic Institute
pp. 278-279

A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface (PDF)

Hau T. Ngo , Old Dominion University
Rajkiran Gottumukkal , Old Dominion University
Vijayan K. Asari , Old Dominion University
pp. 280-281

A High Performance Hybrid Wave-Pipelined Multiplier (PDF)

Jos? G. Delgado-Frias , Washington State University
Suryanarayana B. Tatapudi , Washington State University
pp. 282-283

Towards Integration of Quadratic Placement and Pin Assignment (Abstract)

Patrick Groeneveld , Eindhoven University of Technology
Jurjen Westra , Eindhoven University of Technology
pp. 284-286

Balancing System Level Pipelines with Stage Voltage Scaling (Abstract)

Hui Guo , University of New South Wales
Sri Parameswaran , University of New South Wales
pp. 287-289

Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator (PDF)

D. Dalton , University College Dublin
A. Maili , Graz University of Technology
R. Wei? , Graz University of Technology
R. Quigley , University College Dublin
C. Steger , Graz University of Technology
pp. 290-291

Design of a QCA Memory with Parallel Read/Serial Write (Abstract)

S. Pontarelli , University of Rome
V. Vankamamidi , Northeastern University Boston
M. Ottavi , Northeastern University Boston
A. Salsano , University of Rome
F. Lombardi , Northeastern University Boston
pp. 292-294

RG-SRAM: A Low Gate Leakage Memory Design (PDF)

Praveen Elakkumanan , State University of New York at Buffalo
Ramalingam Sridhar , State University of New York at Buffalo
Charan Thondapu , State University of New York at Buffalo
pp. 295-296

Increasing Data TLB Resilience to Transient Errors (PDF)

Mahmut Kandemir , Pennsylvania State University
Feihui Li , Pennsylvania State University
pp. 297-298

RITC: Repeater Insertion with Timing Target Compensation (PDF)

Xun Liu , North Carolina State University
Yuantao Peng , North Carolina State University
pp. 299-300

Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach (PDF)

Vijayan K. Asari , Old Dominion University
Hau Ngo , Old Dominion University
Adam Livingston , Old Dominion University
Li Tao , Old Dominion University
Ming Zhang , Old Dominion University
pp. 301-302

An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels (PDF)

Ming Z. Zhang , Old Dominion University
Vijayan K. Asari , Old Dominion University
Adam R. Livingston , Old Dominion University
Hau T. Ngo , Old Dominion University
pp. 303-304

A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation (PDF)

Oswaldo Cadenas , University of Reading
Daniel Jones , University of Reading
Graham Megson , University of Reading
pp. 305-306

A Hierachical Method for Wiring and Congestion Prediction (PDF)

Fei He , Tsinghua University
Jiaguang Sun , Tsinghua University
Ming Gu , Tsinghua University
Guowu Yang , Portland State University
Lerong Cheng , University of California at Los Angeles
Zhiwei Tang , Portland State University
Xiaoyu Song , Portland State University
pp. 307-308

CMOS Realization of Online Testable Reversible Logic Gates (PDF)

J. P. Parkerson , University of Arkansas
P. K. Lala , University of Arkansas
D. P. Vasudevan , University of Arkansas
pp. 309-310

A Scalable Parallel SoC Architecture for Network Processors (Abstract)

J?rg-Christian Niemann , University of Paderborn
Mario Porrmann , University of Paderborn
Ulrich R?ckert , University of Paderborn
pp. 311-313

A Comparative Study on Dicing of Multiple Project Wafers (PDF)

Rung-Bin Lin , Yuan Ze University
Meng-Chiou Wu , Yuan Ze University
pp. 314-315
Author Index

Author Index (PDF)

pp. 317-319
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