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2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2005)
Tampa, Florida
May 11, 2005 to May 12, 2005
ISBN: 0-7695-2365-X
pp: 130-135
M. A. Thornton , Southern Methodist University
L. Li , Southern Methodist University
Alex Fit-Florea , Southern Methodist University
D. W. Matula , Southern Methodist University
We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2^k. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2^k operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k=8, 16, 32, and 64.
M. A. Thornton, L. Li, Alex Fit-Florea, D. W. Matula, "Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k", 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), vol. 00, no. , pp. 130-135, 2005, doi:10.1109/ISVLSI.2005.35
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