The Community for Technology Leaders
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2004)
Lafayette, Louisiana
Feb. 19, 2004 to Feb. 20, 2004
ISBN: 0-7695-2097-9
TABLE OF CONTENTS
Introduction
Emerging Trends in VLSI Systems

Decoding of Stochastically Assembled Nanoarrays (Abstract)

Benjamin Gojman , Brown University
John E. Savage , Brown University
Eric Rachlin , Brown University
pp. 11

A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking (Abstract)

Lun Li , Southern Methodist University
Stephen A. Szygenda , Southern Methodist University
Mitchell A. Thornton , Southern Methodist University
pp. 32
System Level Design

System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures (Abstract)

Krishnan Srinivasan , Arizona State University
Nagender Telkar , Arizona State University
Karam S. Chatha , Arizona State University
Vijay Ramamurthi , Arizona State University
pp. 39

Fault Tolerant Algorithms for Network-On-Chip Interconnect (Abstract)

M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
G. M. Link , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
R. R. Brooks , Pennsylvania State University
M. Pirretti , Pennsylvania State University
pp. 46

A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study (Abstract)

Suryaprasad Jayadevappa , Florida Atlantic University
Imad Mahgoub , Florida Atlantic University
Ravi Shankar , Florida Atlantic University
pp. 52
System-on-a-Chip Design

Energy Evaluation Methodology for Platform Based System-on-Chip Design (Abstract)

Tughrul Arslan , The Institute for System Level Integration and University of Edinburgh
Ahmet T. Erdogan , University of Edinburgh
Kristian Hildingsson , The Institute for System Level Integration
pp. 61

Comparison between Different Data Buses Configurations (Abstract)

D. Deschacht , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier
A. Lopez , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier
pp. 69
Advanced VLSI Design

Evaluating Alternative Implementations for LDPC Decoder Check Node Function (Abstract)

M. J. Irwin , Pennsylvania State University
G. Link , Pennsylvania State University
T. Theocharides , Pennsylvania State University
E. Swankoski , Pennsylvania State University
H. Schmit , Carnegie Mellon University
N. Vijaykrishnan , Pennsylvania State University
pp. 77

Minimum Area Cost for a 30 to 70 Gbits/s AES Processor (Abstract)

Ingrid Verbauwhede , University of California at Los Angeles
Alireza Hodjat , University of California at Los Angeles
pp. 83

A Review of Large Parallel Counter Designs (Abstract)

Earl E. Swartzlander, Jr. , University of Texas at Austin
pp. 89

Behavioural Scheduling to Balance the Bit-Level Computational Effort (Abstract)

R. Ruiz-Sautua , Universidad Complutense de Madrid
M. C. Molina , Universidad Complutense de Madrid
J. M. Mend?as , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 99
VLSI Circuits and Systems

New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circuits (Abstract)

Magdy Bayoumi , University of Louisiana at Lafayette
Walid Elgharbawy , University of Louisiana at Lafayette
pp. 115

Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling (Abstract)

Hannu Tenhunen , Royal Institute of Technology
Adam Strak , Royal Institute of Technology
pp. 121

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach (Abstract)

Said Al-Sarawi , University of Adelaide
Peter Celinski , University of Adelaide
Stamatis Vassiliadis , Delft University of Technology
Derek Abbott , University of Adelaide
Sorin Cotofana , Delft University of Technology
pp. 127
Low Power VLSI System Design

Experimental Evaluation of Resonant Clock Distribution (Abstract)

Conrad H. Ziesler , University of Michigan
Marios C. Papaefthymiou , University of Michigan
Juang-ying Chueh , University of Michigan
pp. 135

A Double-Edge Implicit-Pulsed Level Convert Flip-Flop (Abstract)

Magdy Bayoumi , University of Louisiana at Lafayette
Peiyi Zhao , University of Louisiana at Lafayette
Golconda Pradeep Kumar , University of Louisiana at Lafayette
C. Archana , University of Louisiana at Lafayette
pp. 141

Fixed-Load Energy Recovery Memory for Low Power (Abstract)

Conrad H. Ziesler , University of Michigan
Joohee Kim , University of Michigan
pp. 145

Multi-Parameter Power Minimization of Synthesized Datapaths (Abstract)

Ambarish M. Sule , North Carolina State University
W. Rhett Davis , North Carolina State University
Hao Hua , North Carolina State University
pp. 151

Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units (Abstract)

Suhwan Kim , IBM Thomas J. Watson Research Center
Sangjin Hong , State University of New York at Stony Brook
Shu-Shin Chin , State University of New York at Stony Brook
pp. 158
Novel Test Techniques

Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs (Abstract)

Janak H. Patel , University of Illinois at Urbana-Champaign
Mihir A. Shah , University of Illinois at Urbana-Champaign
pp. 167

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST (Abstract)

Kumar N. Dwarakanath , Carnegie Mellon University
Krishnendu Chakrabarty , Duke University
Chunsheng Liu , University of Nebraska-Lincoln
Ronald D. (Shawn) Blanton , Carnegie Mellon University
pp. 173

Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints (Abstract)

Kazuaki Murakami , Kyushu University
Makoto Sugihara , Institute of Systems & Information Technologies/KYUSHU
Yusuke Matsunaga , Kyushu University
pp. 179
Physical Design, Synthesis and Optimization

Control and Data Flow Graph Extraction for High-Level Synthesis (Abstract)

Abdel Ejnioui , University of Central Florida
Ravi Namballa , University of South Florida
N. Ranganathan , University of South Florida
pp. 187

Force-Directed Performance-Driven Placement Algorithm for FPGAs (Abstract)

Wai-Kei Mak , University of South Florida
Hao Li , University of South Florida
Srinivas Katkoori , University of South Florida
pp. 193

Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies (Abstract)

Alex Doboli , State University of New York Stonybrook
Sankalp Kallakuri , State University of New York Stonybrook
Simona Doboli , Hofstra University
pp. 199
Poster Papers

DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems (Abstract)

P. R. Mukund , Rochester Institute of Technology
Ghanshyam Nayak , Rochester Institute of Technology
T. M. Rao , State University of New York at Brockport
Tejasvi Das , Rochester Institute of Technology
pp. 207

Low Power 2.5 Gb/s Serializer for SOC Applications (PDF)

M. Syrzycki , Simon Fraser University
K. Iniewski , Simon Fraser University
pp. 211

A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO (PDF)

Jo Yi Foo , Iowa State University
Robert J. Weber , Iowa State University
Jie Long , Iowa State University
pp. 213

Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation (Abstract)

Tughrul Arslan , University of Edinburgh and Institute for System Level Integration
Indrajit Atluri , University of Edinburgh
pp. 215

A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 ?m, PD SOI Process (Abstract)

Herbert L. Hess , University of Idaho
David Cox , University of Idaho
Erik J. Mentze , University of Idaho
Mohammad Mojarradi , California Institute of Technology
Kevin M. Buck , University of Idaho
pp. 218

Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs (Abstract)

A. Benkrid , Queen?s University of Belfast
D. Crookes , Queen?s University of Belfast
K. Benkrid , Queen?s University of Belfast
pp. 222

Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm (Abstract)

A. T. Erdogan , University of Edinburgh
T. Arslan , University of Edinburgh and Institute for System Level Integration
pp. 226

A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs (Abstract)

S. Sukhsawas , Queen?s University Belfast
K. Benkrid , Queen?s University Belfast
pp. 229

Congestion Estimation for 3D Routing (PDF)

William N. N. Hung , Portland State University
Lerong Cheng , Portland State University
Xiaoyu Song , Portland State University
Guowu Yang , Portland State University
pp. 239

Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models (PDF)

Sandeep K. Shukla , Virginia Polytechnic Institute and State University
Hiren D. Patel , Virginia Polytechnic Institute and State University
pp. 241

Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits (Abstract)

Masanori Hariyama , Tohoku University
Weisheng Chong , Tohoku University
Michitaka Kameyama , Tohoku University
pp. 243

Incorporating Power Reduction Mechanism in Arithmetic Core Design (PDF)

Sangjin Hong , State University of New York at Stony Brook
Shu-Shin Chin , State University of New York at Stony Brook
pp. 249

Multioperand Decimal Addition (Abstract)

Robert D. Kenney , University of Wisconsin-Madison
Michael J. Schulte , University of Wisconsin-Madison
pp. 251

Pipeline Design Based on Self-Resetting Stage Logic (Abstract)

Abdelhalim Alsharqawi , University of Central Florida
Abdel Ejnioui , University of Central Florida
pp. 254

Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths (PDF)

Chandramouli Gopalakrishnan , University of South Florida
Srinivas Katkoori , University of South Florida
pp. 260

On the Reduction of Simultaneous Switching in SoCs (PDF)

Arindam Mukherjee , University of North Carolina at Charlotte
pp. 262

OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip (PDF)

Nattawut Thepayasuwan , State University of New York at Stony Brook
Alex Doboli , State University of New York at Stony Brook
pp. 264

A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture (PDF)

Manfred Glesner , Darmstadt University of Technology
Claude Stötzler , Darmstadt University of Technology
Peter Zipf , Darmstadt University of Technology
pp. 266

Handling Data Streams while Compiling C Programs onto Hardware (PDF)

Rajarshi Mukherjee , Northwestern University
Prith Banerjee , Northwestern University
Alex Jones , University of Pittsburgh
pp. 271

A Subword-Parallel Multiplication and Sum-of-Squares Unit (PDF)

Michael J. Schulte , University of Wisconsin-Madison
John Glossner , Sandbridge Technologies
Shankar Krithivasan , University of Wisconsin-Madison
pp. 273

Hybrid Parallel Counters — Domino and Threshold Logic (PDF)

Said F. Al-Sarawi , University of Adelaide
Michael J. Liebelt , University of Adelaide
Troy D. Townsend , University of Adelaide
Peter Celinski , University of Adelaide
pp. 275

Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters (PDF)

Kenneth Fazel , Southern Methodist University
Peter-Michael Seidel , Southern Methodist University
pp. 277

A Memory Aware High Level Synthesis Tool (PDF)

Nathalie Julien , University of South-Brittany
Eric Senn , University of South-Brittany
Gwenol? Corre , University of South-Brittany
Eric Martin , University of South-Brittany
pp. 279

Scan Cell Ordering for Low Power BIST (Abstract)

Dimitris Nikolos , Research Academic Computer Technology Institute
Dimitris Bakalis , Research Academic Computer Technology Institute
Maciej Bellos , University of Patras
pp. 281

An Efficient Test Vector Ordering Method for Low Power Testing (Abstract)

X. Kavousianos , University of Ioannina
D. Nikolos , University of Patras and Research Academic Computer Technology Institute
M. Bellos , University of Patras and Research Academic Computer Technology Institute
D. Bakalis , University of Patras and Research Academic Computer Technology Institute
pp. 285

CMOS Analog Programmable Logic Array (PDF)

Adrián Núñez-Aldana , Syracuse University
Chandrasekar Rajagopal , Syracuse University
pp. 291

Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications (Abstract)

A. Arapoyanni , University of Athens
S. Matakias , University of Athens
Y. Tsiatouhas , University of Ioannina
Th. Haniotakis , Southern Illinois University
pp. 293

A 64-bit Decimal Floating-Point Adder (PDF)

Nandini Karra , University of Wisconsin-Madison
John Thompson , University of Wisconsin-Madison
Michael J. Schulte , University of Wisconsin-Madison
pp. 297

Parallel Programmable Finite Field GF(2<sup>m</sup>) Multipliers (Abstract)

Nick Iliev , Illinois Institute of Technology
Nathan Jachimiec , Illinois Institute of Technology
James E. Stine , Illinois Institute of Technology
pp. 299

Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow (PDF)

Magesh Sadasivam , State University of New York at Stony Brook
Sangjin Hong , State University of New York at Stony Brook
pp. 303

Compiler-Directed Data Cache Leakage Reduction (PDF)

Wei Zhang , Southern Illinois University at Carbondale
pp. 305

FPGA Placement and Routing Using Particle Swarm Optimization (PDF)

Venu G. Gudise , University of Missouri-Rolla
Ganesh K. Venayagamoorthy , University of Missouri-Rolla
pp. 307

A Reconfigurable Memory Management Core for Java Applications (Abstract)

Abdelkader Rhiati , University of Central Florida
Abdel Ejnioui , University of Central Florida
pp. 309

A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder (Abstract)

Karam S. Chatha , Arizona State University
Krishnan Srinivasan , Arizona State University
Vijay Ramamurthi , Arizona State University
pp. 313

FSEL — Selective Predicated Execution for a Configurable DSP Core (Abstract)

U. Hirnschrott , Vienna University of Technology
J. Nurmi , Tampere University of Technology
A. Krall , Vienna University of Technology
C. Panis , Carinthian Tech Institute
W. Lazian , Infineon Technologies
G. Laure , Infineon Technologies
pp. 317

A Spiking Recurrent Neural Network (PDF)

John G. Harris , University of Florida
Yuan Li , University of Florida
pp. 321
Author Index

Author Index (PDF)

pp. 323
97 ms
(Ver )