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2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2002)
Pittsburgh, Pennsylvania
Apr. 25, 2002 to Apr. 26, 2002
ISBN: 0-7695-1486-3

Panels (PDF)

pp. xiii
Emerging Trends in VLSI Systems

VLSI Systems for Embedded Video (Abstract)

Wayne Wolf , Princeton University
Tiehan Lv , Princeton University
Burak Ozer , Princeton University
pp. 0003

Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits (Abstract)

Alice Wang , Massachusetts Institute of Technology
Stephen V. Kosonocky , IBM T.J. Watson Research Center
Anantha P. Chandrakasan , Massachusetts Institute of Technology
pp. 0007
System Level Design

System Design and Power Optimization for Mobile Computers (Abstract)

Matthew Ettus , Carnegie Mellon University
Asim Smailagic , Carnegie Mellon University
pp. 0015

Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications (Abstract)

M. J. Irwin , Pennsylvania State University
M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
I. Kadayif , Pennsylvania State University
pp. 0020

A Low Power High Performance Distributed DCT Architecture (Abstract)

Ahmed Shams , Intel Inc.
Archana Chidanandan , University of Louisiana
Wendi Pan , University of Louisiana
Magdy Bayoumi , University of Louisiana
pp. 0026
Advanced VLSI Design

Optimal Timing for Skew-Tolerant High-Speed Domino Logic (Abstract)

Seong-Ook Jung , University of Illinois at Urbana-Champaign
Steve Kang , University of California at Santa Cruz
Ki-Wook Kim , Pluris Inc.
pp. 0041

Multi-Output Timed Shannon Circuits (Abstract)

Rolf Drechsler , University of Bremen
Mitchell A. Thornton , Mississippi State University
D. Michael Miller , University of Victoria
pp. 0047

Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation (Abstract)

Alexandre Ferreira Tenca , Oregon State University
Cetin Kaya Koç , Oregon State University
Adnan Abdul-Aziz Gutub , Oregon State University
pp. 0053
Low Power VLSI System Design

Impact of Technology Scaling in the Clock System Power (Abstract)

Narayanan Vijaykrishnan , Pennsylvania State University
David Duarte , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
pp. 0059

Datapath Scheduling using Dynamic Frequency Clocking (Abstract)

N. Ranganathan , University of South Florida
Saraju P. Mohanty , University of South Florida
V. Krishna , Agilent Technology
pp. 0065

Temperature Variable Supply Voltage for Power Reduction (Abstract)

Kaveh Shakeri , Georgia Institute of Technology
James D. Meindl , Georgia Institute of Technology
pp. 0071

Force-Directed Scheduling for Dynamic Power Optimization (Abstract)

Srinivas Katkoori , University of South Florida
Suvodeep Gupta , University of South Florida
pp. 0075
VLSI Circuits and Systems

Efficient Adder Circuits Based on a Conservative Reversible Logic Gate (Abstract)

X. Li , Mississippi State University
P.S. Kokate , Mississippi State University
L. Shivakumaraiah , Mississippi State University
M.A. Thornton , Mississippi State University
J.W. Bruce , Mississippi State University
pp. 0083

Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops (Abstract)

Tarek Darwish , University of Louisiana at Lafayette
Magdy Bayoumi , University of Louisiana at Lafayette
Mohamed Elgamel , University of Louisiana at Lafayette
pp. 0089

VLSI Implementation for MAC-Level DWT Architecture (Abstract)

Lan-Rong Dung , National Chiao-Tung University
Shiuh-Rong Huang , National Chiao-Tung University
pp. 0101

Speedup of Self-Timed Digital Systems Using Early Completion (Abstract)

Scott C. Smith , University of Missouri at Rolla
pp. 0107
System-on-a-Chip Design

A Network on Chip Architecture and Design Methodology (Abstract)

Mikael Millberg , Royal Institute of Technology
Juha-Pekka Soininen , VTT Electronics
Johny Öberg , Royal Institute of Technology
Shashi Kumar , Royal Institute of Technology
Martti Forsell , VTT Electronics
Axel Jantsch , Royal Institute of Technology
Ahmed Hemani , Spirea AB
Kari Tiensyrjä , VTT Electronics
pp. 0117

A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression (Abstract)

Jong-Chih Chien , University of Pittsburgh
C. C. Li , University of Pittsburgh
David P. Birch , University of Pittsburgh
Henry Y.H. Chuang , University of Pittsburgh
Li-Chang Liu , University of Pittsburgh
Steve P. Levitan , University of Pittsburgh
pp. 0125
Physical Design, Synthesis, and Optimization

Accelerating Retiming Under the Coupled-Edge Timing Model (Abstract)

Wolfgang Kunz , University of Kaiserslautern
Kolja Sulimma , University of Kaiserslautern
Ingmar Neumann , University of Kaiserslautern
pp. 0135

Automated Synthesis of Standard Cells using Genetic Algorithms (Abstract)

Benjamin Bishop , University of Georgia
Anil Bahuman , University of Georgia
Khaled Rasheed , University of Georgia
pp. 0141
Test and Verification

Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation (Abstract)

Markus Wedler , University of Kaiserslautern
Dominik Stoffel , University of Kaiserslautern
Wolfgang Kunz , University of Kaiserslautern
pp. 0151

An Efficient Partitioning Algorithm of Combinational CMOS Circuits (Abstract)

Khaled Dib , Universityof Minnesota at Duluth
Bassam Shaer , Universityof Minnesota at Duluth
pp. 0159

A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test (Abstract)

Srdjan Dragic , University of Alberta
Martin Margala , University of Rochester
pp. 0165

Author Index (PDF)

pp. 0171
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