2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2002)

Pittsburgh, Pennsylvania

Apr. 25, 2002 to Apr. 26, 2002

ISBN: 0-7695-1486-3

pp: 0053

Alexandre Ferreira Tenca , Oregon State University

Cetin Kaya Koç , Oregon State University

Adnan Abdul-Aziz Gutub , Oregon State University

ABSTRACT

Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montgomery modular inverse operation. The implementations are based on the same inversion algorithm, however, one is fixed (fully parallel) and the other is scalable. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate within better or similar speed. Both hardware designs are compared based on their speed and area. The area of the scalable design is on average 42% smaller than the fixed one. The delay of the designs, however, depends on the actual data size and the maximum numbers the hardware can handle. As the actual data size approach the hardware limit the scalable hardware speedup reduces in comparison to the fixed one, but still its delay is practical.

INDEX TERMS

VLSI Application-Specific inversion systems, Scalable architecture, Modular arithmetic, Modular inversion hardware, Montgomery multiplication, Almost Montgomery inverse, Cryptography, Extended Euclidean algorithm

CITATION

Alexandre Ferreira Tenca,
Cetin Kaya Koç,
Adnan Abdul-Aziz Gutub,
"Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation",

*2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, vol. 00, no. , pp. 0053, 2002, doi:10.1109/ISVLSI.2002.1016874SEARCH