The Community for Technology Leaders
15th International Symposium on System Synthesis (2002)
Kyoto, Japan
Oct. 2, 2002 to Oct. 4, 2002
ISBN: 1-58113-576-9
TABLE OF CONTENTS

A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units (PDF)

B. Middha , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
V. Raj , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
A. Gangwar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
A. Kumar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
M. Balakrishnan , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
pp. 2-7

Tuning of loop cache architectures to programs in embedded system design (PDF)

S. Cotterell , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
pp. 8-13

Combined functional partitioning and communication speed selection for networked voltage-scalable processors (PDF)

Jinfeng Liu , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
P.H. Chou , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Bagherzadeh , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 14-19

Optimal message-passing for data coherency in distributed architecture (PDF)

Junyu Peng , Center For Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 20-25

Unifying memory and processor wrapper architecture in multiprocessor SoC design (PDF)

F. Gharsalli , Lab. TIMA, Grenoble, France
D. Lyonnard , Lab. TIMA, Grenoble, France
A. Meftali , Lab. TIMA, Grenoble, France
F. Rousseau , Lab. TIMA, Grenoble, France
A.A. Jerraya , Lab. TIMA, Grenoble, France
pp. 26-31

An accelerated datapath width optimization scheme for area reduction of embedded systems (PDF)

M.M. Uddin , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Kasuga, Japan
Y. Cao , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Kasuga, Japan
H. Yasuura , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Kasuga, Japan
pp. 32-37

Controller estimation for FPGA target architectures during high-level synthesis (PDF)

C. Menn , FZI Forschungszentrum Informatik, Karlsruhe, Germany
O. Bringmann , FZI Forschungszentrum Informatik, Karlsruhe, Germany
pp. 56-61

System-level modeling of a network switch SoC (PDF)

J.M. Paul , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
C.P. Andrews , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A.S. Cassidy , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 62-67

System-level design of IEEE1394 bus segment bridge (PDF)

H. Yamamoto , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
K. Chikamura , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
A. Shigiya , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
K. Tsujino , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
T. Izumi , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
T. Onoye , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
Y. Nakamura , Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
pp. 74-79

Security-driven exploration of cryptography in DSP cores (PDF)

C.H. Gebotys , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 80-85

A case study of hardware and software synthesis in ForSyDe (PDF)

Zhonghai Lu , R. Inst. of Technol., Stockholm, Sweden
I. Sander , R. Inst. of Technol., Stockholm, Sweden
A. Jantsch , R. Inst. of Technol., Stockholm, Sweden
pp. 86-91

An adaptive low-power transmission scheme for on-chip networks (PDF)

F. Worm , Archit. Lab., Ecole Polytech. Fed. de Lausanne, Switzerland
P. Ienne , Archit. Lab., Ecole Polytech. Fed. de Lausanne, Switzerland
pp. 92-100

CMP on SoC: architect's view (PDF)

S. Sakai , Univ. of Tokyo, Japan
pp. 101-102

Managing dynamic concurrent tasks in embedded real-time multimedia systems (PDF)

Peng Yang , Kapeldreef 75, Leuven, Belgium
P. Marchal , Kapeldreef 75, Leuven, Belgium
Chun Wong , Kapeldreef 75, Leuven, Belgium
pp. 112-119

A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design (PDF)

A. Halambi , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Shrivastava , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
P. Biswas , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 120-125

Timing analysis of embedded software for speculative processors (PDF)

T. Mitra , Sch. of Comput., Nat. Univ. of Singapore, Singapore
A. Roychoudhury , Sch. of Comput., Nat. Univ. of Singapore, Singapore
Xianfeng Li , Sch. of Comput., Nat. Univ. of Singapore, Singapore
pp. 126-131

Code compression for VLIW processors using variable-to-fixed coding (PDF)

Yuan Xie , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 138-143

Optimal code size reduction for software-pipelined and unfolded loops (PDF)

Qingfeng Zhuge , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Bin Xiao , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Zili Shao , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
E.H.-M. Sha , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
pp. 144-149

Formal verification in a component-based reuse methodology (PDF)

D. Karlsson , IDA, Linkoping Univ., Sweden
P. Eles , IDA, Linkoping Univ., Sweden
Zebo Peng , IDA, Linkoping Univ., Sweden
pp. 156-161

Validation in a component-based design flow for multicore SoCs (PDF)

G. Nicolescu , TIMA Lab., SLS Group, Grenoble, France
Sungjoo Yoo , TIMA Lab., SLS Group, Grenoble, France
A. Bouchhima , TIMA Lab., SLS Group, Grenoble, France
A.A. Jerraya , TIMA Lab., SLS Group, Grenoble, France
pp. 162-167

Efficient simulation of synthesis-oriented system level designs (PDF)

N. Savoiu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
S.K. Shukla , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
R.K. Gupta , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 168-173

Virtual synchronization for fast distributed cosimulation of dataflow task graphs (PDF)

Dohyung Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Chan-Eun Rhee , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Youngmin Yi , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Sungchan Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Hyunguk Jung , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Soonhoi Ha , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 174-179

A new performance evaluation approach for system level design space exploration (PDF)

C.P. Joshi , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
A. Kumar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
M. Balakrishnan , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India
pp. 180-185

Special session: security on SoC (Abstract)

C. Gebotys , Waterloo Univ., Ont., Canada
pp. 192-194

Securing wireless data: system architecture challenges (PDF)

S. Ravi , Comput. & Commun. Res. Labs, NEC USA, Princeton, NJ, USA
A. Raghunathan , Comput. & Commun. Res. Labs, NEC USA, Princeton, NJ, USA
N. Potlapally , Comput. & Commun. Res. Labs, NEC USA, Princeton, NJ, USA
pp. 195-200

Data memory design considering effective bitwidth for low-energy embedded systems (PDF)

Y. Cao , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Tomiyama , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
T. Okuma , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
H. Yasuura , Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
pp. 201-206

Efficient power reduction techniques for time multiplexed address buses (PDF)

M. Mamidipaka , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 207-212

Reducing energy consumption by dynamic copying of instructions onto onchip memory (PDF)

S. Steinke , Dept. of Comput. Sci., Dortmund Univ., Germany
N. Grunwald , Dept. of Comput. Sci., Dortmund Univ., Germany
L. Wehmeyer , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 213-218

Low-power data memory communication for application-specific embedded processors (PDF)

P. Petrov , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 219-224

System-level abstraction semantics (PDF)

A. Gerstlauer , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
D.D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 231-236

Round-robin Arbiter Design and Generation (PDF)

E.S. Shin , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
V.J. Mooney , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
G.F. Riley , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 243-248

An object-oriented design process for system-on-chip using UML (PDF)

Qiang Zhu , Fujitsu Labs. Ltd., Kawasaki, Japan
A. Matsuda , Fujitsu Labs. Ltd., Kawasaki, Japan
S. Kuwamura , Fujitsu Labs. Ltd., Kawasaki, Japan
T. Nakata , Fujitsu Labs. Ltd., Kawasaki, Japan
pp. 249-254

Dynamic common sub-expression elimination during scheduling in high-level synthesis (PDF)

S. Gupta , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
M. Reshadi , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Savoiu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
N. Duff , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
R. Gupta , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
A. Nicolau , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 261-266

Author index (PDF)

pp. 267-268
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