The Community for Technology Leaders
System Synthesis, International Symposium on (2002)
Kyoto, Japan
Oct. 2, 2002 to Oct. 4, 2002
ISBN: 1-58113-576-9
TABLE OF CONTENTS
Keynote
Processor-Based System

A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units (Abstract)

M. Balakrishnan , Indian Institute of Technology Delhi, India
Anshul Kumar , Indian Institute of Technology Delhi, India
Anup Gangwar , Indian Institute of Technology Delhi, India
Paolo Ienne , Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Bhuvan Middha , Indian Institute of Technology Delhi, India
pp. 2-7

Tuning of Loop Cache Architectures to Programs in Embedded System Design (Abstract)

Frank Vahid , University of California, Riverside and the Center for Embedded Computer Systems at UC Irvine
Susan Cotterell , University of California, Riverside
pp. 8-13

Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors (Abstract)

Jinfeng Liu , University of California, Irvine, CA
Pai H. Chou , University of California, Irvine, CA
Nader Bagherzadeh , University of California, Irvine, CA
pp. 14-19

Optimal Message-Passing for Data Coherency in Distributed Architecture (Abstract)

Junyu Peng , University of California, Irvine, CA
Daniel Gajski , University of California, Irvine, CA
pp. 20-25

Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design (Abstract)

Fr?d?ric Rousseau , Laboratoire TIMA, Grenoble cedex, France
Damien Lyonnard , Laboratoire TIMA, Grenoble cedex, France
F?rid Gharsalli , Laboratoire TIMA, Grenoble cedex, France
Ahmed A. Jerraya , Laboratoire TIMA, Grenoble cedex, France
Samy Meftali , Laboratoire TIMA, Grenoble cedex, France
pp. 26-31

An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems (Abstract)

Mohammad Mesbah Uddin , Kyushu University, Kasuga, Japan
Yun Cao , Kyushu University, Kasuga, Japan
Hiroto Yasuura , Kyushu University, Kasuga, Japan
pp. 32-37
Reconfigurable System

Datapath Merging and Interconnection Sharing for Reconfigurable Architectures (Abstract)

Zhining Huang , Princeton University, Princeton, NJ
Sharad Malik , Princeton University, Princeton, NJ
Nahri Moreano , DCT-UFMS, Campo Grande, MS, Brazil
Guido Araujo , IC-UNICAMP, Campinas, SP, Brazil
pp. 38-43

A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor (Abstract)

Carles Rodoreda Sala , Sony Espa?a S.A. Design Division, Viladecavalls - Barcelona, Spain
Natalino G. Bus? , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 44-49

Energy/Power Estimation of Regular Processor Arrays (Abstract)

Steven Derrien , IRISA, France
Sanjay Rajopadhye , Colorado State University
pp. 50-55

Controller Estimation for FPGA Target Architectures during High-Level Synthesis (Abstract)

Wolfgang Rosenstiel , Universit?t T?bingen, T?bingen, Germany
Oliver Bringmann , FZI Forschungszentrum Informatik, Karlsruhe, Germany
Carsten Menn , FZI Forschungszentrum Informatik, Karlsruhe, Germany
pp. 56-61
Practical Experiences

System-Level Modeling of a Network Switch SoC (Abstract)

JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Christopher P. Andrews , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
Andrew S. Cassidy , Carnegie Mellon University, Pittsburgh, PA
pp. 62-67

Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study (Abstract)

E. A. de Kock , Philips Research, Eindhoven, The Netherlands
pp. 68-73

System-Level Design of IEEE1394 Bus Segment Bridge (Abstract)

Keishi Chikamura , Kyoto University, Kyoto, Japan
Hirofumi Yamamoto , Kyoto University, Kyoto, Japan
Atsuhito Shigiya , Kyoto University, Kyoto, Japan
Kosuke Tsujino , Kyoto University, Kyoto, Japan
Tomonori Izumi , Kyoto University, Kyoto, Japan
Takao Onoye , Kyoto University, Kyoto, Japan
Yukihiro Nakamura , Kyoto University, Kyoto, Japan
pp. 74-79

Security-Driven Exploration of Cryptography in DSP Cores (Abstract)

Catherine H. Gebotys , University of Waterloo, Waterloo, Canada
pp. 80-85

A Case Study of Hardware and Software Synthesis in ForSyDe (Abstract)

Zhonghai Lu , Royal Institute of Technology, Stockholm, Sweden
Ingo Sander , Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
pp. 86-91
Special Session on On-Chip Multi-Processing

An Adaptive Low-Power Transmission Scheme for On-Chip Networks (Abstract)

Patrick Thiran , EPFL, Lausanne, Switzerland
Fr?d?ric Worm , EPFL, Lausanne, Switzerland
Giovanni De Micheli , Stanford University, Calif., USA
Paolo Ienne , EPFL, Lausanne, Switzerland
pp. 92-100

CMP on SoC: Architect's View (PDF)

Shuichi Sakai , The University of Tokyo, Tokyo, Japan
pp. 101-102
Invited Talk

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems (Abstract)

Peng Yang , K.U.Leuven-ESAT
Francky Catthoor , K.U.Leuven-ESAT
Patrick David , K.U.Leuven-ESAT
Paul Marchal , K.U.Leuven-ESAT
Rudy Lauwereins , K.U.Leuven-ESAT
Chun Wong , K.U.Leuven-ESAT
Stefaan Himpe , K.U.Leuven-ESAT
Johan Vounckx , K.U.Leuven-ESAT
pp. 112-119
Design Methedologies Based on Instruction Code

A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design (Abstract)

Ashok Halambi , University of California, Irvine, California
Nikil Dutt , University of California, Irvine, California
Aviral Shrivastava , University of California, Irvine, California
Alex Nicolau , University of California, Irvine, California
Partha Biswas , University of California, Irvine, California
pp. 120-125

Timing Analysis of Embedded Software for Speculative Processors (Abstract)

Xianfeng Li , National University of Singapore, Republic of Singapore
Abhik Roychoudhury , National University of Singapore, Republic of Singapore
Tulika Mitra , National University of Singapore, Republic of Singapore
pp. 126-131

Modeling Assembly Instruction Timing in Superscalar Architectures (Abstract)

V. Trianni , Politecnico di Milano, Piazza L. da Vinci, Milano, Italy
F. Salice , Politecnico di Milano, Piazza L. da Vinci, Milano, Italy
D. Sciuto , Politecnico di Milano, Piazza L. da Vinci, Milano, Italy
C. Brandolese , Politecnico di Milano, Piazza L. da Vinci, Milano, Italy
W. Fornaciari , Politecnico di Milano, Piazza L. da Vinci, Milano, Italy
G. Beltrame , CEFRIEL Research Centre, Via R. Fucini, Milano, Italy
pp. 132-137

Code Compression for VLIW Processors Using Variable-to-Fixed Coding (Abstract)

Haris Lekatsas , NEC USA, Princeton, NJ, USA
Wayne Wolf , Princeton University, Princeton, NJ, USA
Yuan Xie , Princeton University, Princeton, NJ, USA
pp. 138-143

Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops (Abstract)

Zili Shao , University of Texas at Dallas, Richardson, Texas
Bin Xiao , University of Texas at Dallas, Richardson, Texas
Edwin H.-M. Sha , University of Texas at Dallas, Richardson, Texas
Chantana Chantrapornchai , Silpakorn University, Nakorn Pathom, Thailand
Qingfeng Zhuge , University of Texas at Dallas, Richardson, Texas
pp. 144-149
Simulation and Verification

The Formal Execution Semantics of SpecC (Abstract)

Wolfgang Mueller , Paderborn University, Paderborn, Germany
Andreas Gerstlauer , University of California, Irvine, USA
Rainer D?mer , University of California, Irvine, USA
pp. 150-155

Formal Verification in a Component-Based Reuse Methodology (Abstract)

Daniel Karlsson , IDA, Linkopings universitet, 581 83 Linkoping, Sweden
Zebo Peng , IDA, Linkopings universitet, 581 83 Linkoping, Sweden
Petru Eles , IDA, Linkopings universitet, 581 83 Linkoping, Sweden
pp. 156-161

Validation in a Component-Based Design Flow for Multicore SoCs (Abstract)

Gabriela Nicolescu , SLS Group, TIMA Laboratory, Grenoble, France
Sungjoo Yoo , SLS Group, TIMA Laboratory, Grenoble, France
Ahmed Amine Jerraya , SLS Group, TIMA Laboratory, Grenoble, France
Aimen Bouchhima , SLS Group, TIMA Laboratory, Grenoble, France
pp. 162-167

Efficient Simulation of Synthesis-Oriented System Level Designs (Abstract)

Nick Savoiu , University of California, Irvine, California
Rajesh K. Gupta , University of California, Irvine, California
Sandeep K. Shukla , University of California, Irvine, California
pp. 168-173

Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs (Abstract)

Sungchan Kim , Seoul National Univ., Seoul, Korea
Hyunguk Jung , Seoul National Univ., Seoul, Korea
Soonhoi Ha , Seoul National Univ., Seoul, Korea
Dohyung Kim , Seoul National Univ., Seoul, Korea
Youngmin Yi , Seoul National Univ., Seoul, Korea
Chan-Eun Rhee , Seoul National Univ., Seoul, Korea
pp. 174-179

A New Performance Evaluation Approach for System Level Design Space Exploration (Abstract)

C. P. Joshi , Indian Institute of Technology Delhi, India
M. Balakrishnan , Indian Institute of Technology Delhi, India
Anshul Kumar , Indian Institute of Technology Delhi, India
pp. 180-185

A Visual Approach to Validating System Level Designs (Abstract)

Thomas Kropf , University of T?bingen
J? Ruf , University of T?bingen
Jochen Klose , University of Oldenburg
pp. 186-191
Special Session on Security on SoC

Special Session: Security on SoC (Abstract)

Naofumi Takagi , Nagoya University, Japan
Cathy Gebotys , University of Waterloo, Canada
Hiroto Yasuura , Kyushu University, Japan
Michael Torla , Motorola
pp. 192-194

Securing Wireless Data: System Architecture Challenges (Abstract)

Anand Raghunathan , NEC USA, Princeton, NJ
Nachiketh Potlapally , NEC USA, Princeton, NJ
Srivaths Ravi , NEC USA, Princeton, NJ
pp. 195-200
Low Power Memory System

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems (Abstract)

Takanori Okuma , Kyushu University, Fukuoka 816-8580, Japan
Yun Cao , Kyushu University, Fukuoka 816-8580, Japan
Hiroto Yasuura , Kyushu University, Fukuoka 816-8580, Japan
Hiroyuki Tomiyama , Institute of Systems&Information Technologies, Momochihama, Fukuoka 814-0001, Japan
pp. 201-206

Efficient Power Reduction Techniques for Time Multiplexed Address Buses (Abstract)

Nikil Dutt , Univ. of California, Irvine, CA
Dan Hirschberg , Univ. of California, Irvine, CA
Mahesh Mamidipaka , Univ. of California, Irvine, CA
pp. 207-212

Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory (Abstract)

Rajeshwari Banakar , Indian Institute of Technology, Delhi, India
Stefan Steinke , University of Dortmund, 44221 Dortmund, Germany
Nils Grunwald , University of Dortmund, 44221 Dortmund, Germany
Lars Wehmeyer , University of Dortmund, 44221 Dortmund, Germany
M. Balakrishnan , Indian Institute of Technology, Delhi, India
Peter Marwedel , University of Dortmund, 44221 Dortmund, Germany
pp. 213-218

Low-Power Data Memory Communication for Application-Specific Embedded Processors (Abstract)

Peter Petrov , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 219-224

System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory (Abstract)

Peeter Ellervee , Tallinn Technical University
Vincent J. Mooney , Georgia Institute of Technology
Jun Cheol Park , Georgia Institute of Technology
Kyu-Won Choi , Georgia Institute of Technology
Kiran Puttaswamy , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 225-230
High Level and Architectural Synthesis

System-Level Abstraction Semantics (Abstract)

Andreas Gerstlauer , University of California, Irvine, Irvine, CA
Daniel D. Gajski , University of California, Irvine, Irvine, CA
pp. 231-236

A Symbolic Approach for the Combined Solution of Scheduling and Allocation (Abstract)

Luciano Lavagno , Politecnico di Torino, Turin, ITALY
Gianpiero Cabodi , Politecnico di Torino, Turin, ITALY
Mihai Lazarescu , Cadence Design Systems, Inc., Turin, ITALY
Stefano Quer , Politecnico di Torino, Turin, ITALY
Sergio Nocco , Politecnico di Torino, Turin, ITALY
Claudio Passerone , Politecnico di Torino, Turin, ITALY
pp. 237-242

Round-Robin Arbiter Design and Generation (Abstract)

Vincent J. Mooney , Georgia Institute of Technology, Atlanta, GA
Eung S. Shin , Georgia Institute of Technology, Atlanta, GA
George F. Riley , Georgia Institute of Technology, Atlanta, GA
pp. 243-248

An Object-Oriented Design Process for System-on-Chip Using UML (Abstract)

Minoru Shoji , Fujitsu Limited, Kawasaki 211-8588, Japan
Tsuneo Nakata , Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan
Qiang Zhu , Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan
Shinya Kuwamura , Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan
Akio Matsuda , Fujitsu Laboratories Limited, Kawasaki 211-8588, Japan
pp. 249-254

Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors (Abstract)

Francisco Moya , U. of Castilla-La Mancha, Ciudad Real, Spain
Jos? M. Moya , Technical University of Madrid, Madrid, Spain
Fernando Rinc? , U. of Castilla-La Mancha, Ciudad Real, Spain
Juan Carlos L?pez , U. of Castilla-La Mancha, Ciudad Real, Spain
pp. 255-260

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis (Abstract)

Rajesh Gupta , University of California at Irvine
Nick Savoiu , University of California at Irvine
Alex Nicolau , University of California at Irvine
Sumit Gupta , University of California at Irvine
Mehrdad Reshadi , University of California at Irvine
Nikil Dutt , University of California at Irvine
pp. 261-266
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