The Community for Technology Leaders
International Symposium on System Synthesis (2001)
Montreal, Quebec, Canada
Sept. 30, 2001 to Oct. 3, 2001
ISBN: 1-58113-418-5

A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems (Abstract)

O.P. Gangwal , Embedded Syst. Architectures on Silicon, Philips Res. Labs., Netherlands
pp. 1-6

Exploiting scratch-pad memory using Presburger formulas (Abstract)

M. Kandemir , Microsystems Design Lab, Pennsylvania State Univ., University Park, PA, USA
pp. 7-12

APEX: access pattern based memory architecture exploration (Abstract)

P. Grun , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 25-32

Powering networks on chips (Abstract)

L. Benini , DEIS, Bologna Univ., Italy
pp. 33-38

Retargetable static timing analysis for embedded software (PDF)

Kaiyu Chen , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 39-44

RTL semantics and methodology (Abstract)

B. Bailey , Mentor Graphics Corp, Wilsonville, OR, USA
pp. 69-74

SystemC - a modeling platform supporting multiple design abstractions (PDF)

P.R. Panda , Synopsys lnc, Mountain View, CA, USA
pp. 75-80

The standard SpecC language (Abstract)

M. Fujita , Dept. of Electron. Eng., Tokyo Univ., Japan
pp. 81-86

Interoperability as a design issue in C++ based modeling environments (Abstract)

F. Doucet , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 87-92

Bridging the gap between ISA compilers and silicon compilers: a challenge for future SoC design (Abstract)

G.R. Gao , Dept. of Electr. & Comput Eng., Delaware Univ., Newark, DE, USA
pp. 93

Loop fusion for memory space optimization (Abstract)

A. Fraboulet , Inst. Nat. des Sci. Appliquees de Lyon, Villeurbanne, France
pp. 95-100

Cache-efficient memory layout of aggregate data structures (Abstract)

P.R. Panda , Synopsys Inc., Mountain View, CA, USA
pp. 101-106

Data cache energy minimizations through programmable tag size matching to the applications (Abstract)

P. Petrov , Comput. Sci. & Eng. Dept., Univ. of California, San Diego, CA, USA
pp. 113-117

An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling (Abstract)

L.H. Chandrasena , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 124-129

Current consumption dynamics at instruction and program level for a VLIW DSP processor (PDF)

R. Muresan , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 130-135

Efficient instruction-level optimization methodology for low-power embedded systems (PDF)

Kyu-Won choi , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 147-152

Static resource models of instruction sets (Abstract)

Q. Zhao , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 159-164

A data scheduler for multi-context reconfigurable architectures (Abstract)

M. Sanchez-Elez , Dept. de Arquitectura de Computadores y Automatica, Univ. Complutense, Madrid, Spain
pp. 177-182

Scheduling and partitioning for multiple loop nests (PDF)

Zhong Wang , Dept of Comp. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 183-188

Embedded systems technologies for application-specific architecture platforms (Abstract)

P.G. Paulin , Central R&D, STMicroelectronics, Nepean, Ont., Canada
pp. 195

System design of a telecommunication router (Abstract)

R. Norman , Hyperchip Inc., Montreal, Que., Canada
pp. 196

Network processing in content inspection applications (Abstract)

F. Welfeld , Solidum Syst., Ottawa, Ont., Canada
pp. 197-201

Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults (Abstract)

C.-I.H. Chen , Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
pp. 203-208

High-level automatic pipelining for sequential circuits (Abstract)

M.-C.V. Marinescu , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 215-220

Soft-cores generation by instruction set analysis (Abstract)

A. Fin , Dipt. di Informatica, Univ. di Verona, Italy
pp. 227-232

Modeling and simulation of steady state and transient behaviors for emergent SoCs (Abstract)

J.M. Paul , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 262-267

Control and communication performance analysis of embedded DSP systems in the MASIC methodology (Abstract)

A.K. Deb , Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Kista, Sweden
pp. 274-279

Author index (PDF)

pp. 280-281
Panel Discussion

New Design Paradigms: What Needs to be Standardized? (PDF)

M. Fujita , Tokyo University, Japan
P. Panda , Synopsys, USA
R. Gupta , University of California, Irvine, USA
B. Bailey , Mentor Graphics, USA
G. Gao , University of Delaware, Newark, DE
W. Rosenstiel , University of Tubingen, Germany
pp. 94

Programming Models for Network Processors (PDF)

P. Paulin , STMicroelectronics, Ottawa, Canada
Feliks J. Welfeld , Solidum Systems, Ottawa, Canada
R. Norman , Hyperchip Inc., Montr?al, Canada
A. A. Jerraya , TIMA, France
pp. 202
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