The Community for Technology Leaders
System Synthesis, International Symposium on (2001)
Montr?al, P.Q., Canada
Sept. 30, 2001 to Oct. 3, 2001
ISBN: 1-58113-418-5
TABLE OF CONTENTS
Session 1: Memory Optimization Methodologies

A Scalable and Flexible Data Synchronization Scheme for Embedded HW-SW Shared-Memory Systems (Abstract)

Paul Lippens , Philips Research Laboratories, The Netherlands
Andr? Nieuwland , Philips Research Laboratories, The Netherlands
Om Prakash Gangwal , Philips Research Laboratories, The Netherlands
pp. 1-6

Exploiting Scratch-Pad Memory Using Presburger Formulas (Abstract)

Mahmut Kandemir , Pennsylvania State University, University Park, PA
Ugur Sezer , University of Wisconsin, Madison, WI
Ismail Kadayif , Pennsylvania State University, University Park, PA
pp. 7-12

System-Level Interconnect Architecture Exploration for Custom Memory Organizations (Abstract)

Allert van Zelst , Agere Systems, The Netherlands
Arnout Vandecappelle , IMEC vzw, Belgium
Francky Catthoor , IMEC vzw, Belgium
Tycho van Meeuwen , IMEC vzw, Belgium
Diederik Verkest , IMEC vzw, Belgium
pp. 13-18

An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip (Abstract)

Ahmed A. Jerraya , TIMA laboratory, Grenoble cedex, France
Samy Meftali , TIMA laboratory, Grenoble cedex, France
Frederic Rousseau , TIMA laboratory, Grenoble cedex, France
Ferid Gharsalli , TIMA laboratory, Grenoble cedex, France
pp. 19-24

APEX: Access Pattern Based Memory Architecture Exploration (Abstract)

Alex Nicolau , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
Peter Grun , University of California, Irvine, CA
pp. 25-32
Session 2: Keynote

Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs (Abstract)

Luca Benini , Universit? di Bologna, Bologna, Italy
Giovanni De Micheli , Stanford University, Stanford, CA
pp. 33-38
Session 3: H/S Embedded Systems

Retargetable Static Timing Analysis for Embedded Software (Abstract)

Sharad Malik , Princeton University, Princeton, NJ
David I. August , Princeton University, Princeton, NJ
Kaiyu Chen , Princeton University, Princeton, NJ
pp. 39-44

Performance Analysis with Confidence Intervals for Embedded Software Processes (Abstract)

Axel Jantsch , Royal Institute of Technology, Sweden
Per Bjur?us , Saab Avionics, Sweden
pp. 45-50

On-Line Fault Detection in a Hardware/Software Co-Design Environment: System Partitioning (Abstract)

C. Bolchini , Politecnico di Milano, Milano, Italy
L. Pomante , Politecnico di Milano, Milano, Italy
F. Salice , Politecnico di Milano, Milano, Italy
D. Sciuto , Politecnico di Milano, Milano, Italy
pp. 51-56

Using Static Scheduling Techniques for the Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description (Abstract)

Heinrich Meyr , Aachen University of Technology (RWTH), Aachen, Germany
Gunnar Braun , Aachen University of Technology (RWTH), Aachen, Germany
Andreas Hoffmann , Aachen University of Technology (RWTH), Aachen, Germany
Achim Nohl , Aachen University of Technology (RWTH), Aachen, Germany
pp. 57-62

Design and Simulation of a Pipelined Decompression Architecture for Embedded Systems (Abstract)

J? Henkel , NEC USA
Wayne Wolf , Princeton University, Princeton, NJ
Haris Lekatsas , NEC USA
pp. 63-68
Session 4: Special Session on Design Paradigms

RTL Semantics and Methodology (Abstract)

Dan Gajski , University of California, Irvine, CA
Brian Bailey , Mentor Graphics Corp., Wilsonville, OR
pp. 69-74

The Standard SpecC Language (Abstract)

Masahiro Fujita , The University of Tokyo, Tokyo, Japan
Hiroshi Nakamura , The University of Tokyo, Tokyo, Japan
pp. 81-86

Interoperability as a Design Issue in C++ Based Modeling Environments (Abstract)

Patrick Schaumont , University of California, Los Angeles, CA
Masato Otsuka , Fujitsu Ltd., Kawasaki, Japan
Rajesh Gupta , University of California, Irvine, CA
Sandeep Shukla , University of California, Irvine, CA
Frederic Doucet , University of California, Irvine, CA
pp. 87-92
Panel Discussion

New Design Paradigms: What Needs to be Standardized? (PDF)

W. Rosenstiel , University of Tubingen, Germany
R. Gupta , University of California, Irvine, USA
P. Panda , Synopsys, USA
M. Fujita , Tokyo University, Japan
B. Bailey , Mentor Graphics, USA
G. Gao , University of Delaware, Newark, DE
pp. 94
Session 5: Memory Aspects in System Design

Loop Fusion for Memory Space Optimization (Abstract)

Anne Mignotte , Institut National des Sciences Appliqu?es de Lyon, Villeurbanne, France
Antoine Fraboulet , Institut National des Sciences Appliqu?es de Lyon, Villeurbanne, France
Karen Kodary , Institut National des Sciences Appliqu?es de Lyon, Villeurbanne, France
pp. 95-100

Cache-Efficient Memory Layout of Aggregate Data Structures (Abstract)

Luc Semeria , Clearwater Networks Inc., Los Gatos, CA
Giovanni de Micheli , Stanford University, Stanford, CA
Preeti Ranjan Panda , Synopsys Inc., Mountain View, CA
pp. 101-106

Systematic Speed-Power Memory Data-Layout Exploration for Cache Controlled Embedded Multimedia Applications (Abstract)

F. Catthoor , IMEC Lab., Leuven, Belgium and Katholieke Universiteit Leuven, Belgium
C. Kulkarni , IMEC Lab., Leuven, Belgium
M. Miranda , IMEC Lab., Leuven, Belgium
D. Verkest , IMEC Lab., Leuven, Belgium
C. Ghez , IMEC Lab., Leuven, Belgium
pp. 107-112

Data Cache Energy Minimizations through Programmable Tag Size Matching to the Applications (Abstract)

Alex Orailoglu , University of California, San Diego, CA
Peter Petrov , University of California, San Diego, CA
pp. 113-117

Phase Coupled Operation Assignment for VLIW Processors with Distributed Register Files (Abstract)

Marco Bekooij , Philips Research, Eindhoven, The Netherlands
Jochen Jess , University of Technology, Eindhoven, The Netherlands
Jef van Meerbergen , Philips Research, Eindhoven, The Netherlands
pp. 118-123
Session 6: Synthesis for Low Power

An Energy Efficient Rate Selection Algorithm for Voltage Quantized Dynamic Voltage Scaling (Abstract)

Priyadarshana Chandrasena , Adelaide University, Adelaide, Australia
Lama H. Chandrasena , Adelaide University, Adelaide, Australia
Michael J. Liebelt , Adelaide University, Adelaide, Australia
pp. 124-129

Current Consumption Dynamics at Instruction and Program Level for a VLIW DSP Processor (Abstract)

Catherine H. Gebotys , University of Waterloo, Waterloo, Ontario, Canada
Radu Muresan , University of Waterloo, Waterloo, Ontario, Canada
pp. 130-135

Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation (Abstract)

D. Sciuto , Politecnico di Milano
W. Fornaciari , Politecnico di Milano
F. Salice , Politecnico di Milano
G. Beltrame , CEFRIEL
V. Trianni , Politecnico di Milano
C. Brandolese , Politecnico di Milano
pp. 136-141

System Level Optimization and Design Space Exploration for Low Power (Abstract)

Milan Schulte , OFFIS Research Institute
Eike Schmidt , OFFIS Research Institute
Arne Schulz , OFFIS Research Institute
Lars Kruse , OFFIS Research Institute
Alexander Pratsch , OFFIS Research Institute
Ansgar Stammermann , OFFIS Research Institute
Wolfgang Nebel , OFFIS Research Institute
pp. 142-146

Efficient Instruction-Level Optimization Methodology for Low-Power Embedded Systems (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Kyu-won Choi , Georgia Institute of Technology
pp. 147-152

Source Code Transformation Based on Software Cost Analysis (Abstract)

Eui-Young Chung , Stanford University
Giovanni De Micheli , Stanford University
Luca Benini , Universitá di Bologna
pp. 153-158
Session 7: High Level and Architectural Synthesis

Static Resource Models of Instruction Sets (Abstract)

B. Mesman , Philips Research Laboratories, Eindhoven, The Netherlands
Q. Zhao , Eindhoven University of Technology, Eindhoven, The Netherlands
J. A. G. Jess , Eindhoven University of Technology, Eindhoven, The Netherlands
C. A. J. van Eijk , Magma Design Automation
T. Basten , Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 159-164

Combined Instruction and Loop Parallelism in Array Synthesis for FPGAs (Abstract)

Sanjay Rajopadhye , IRISA, Rennes, France
Susmita Sur Kolay , Indian Statistical Institute, Calcutta, India
Steven Derrien , IRISA, Rennes, France
pp. 165-170

Conditional Speculation and Its Effects on Performance and Area for High-Level Synthesis (Abstract)

Nick Savoiu , University of California at Irvine, Irvine, CA
Nikil Dutt , University of California at Irvine, Irvine, CA
Alex Nicolau , University of California at Irvine, Irvine, CA
Sumit Gupta , University of California at Irvine, Irvine, CA
Rajesh Gupta , University of California at Irvine, Irvine, CA
pp. 171-176

A Data Scheduler for Multi-Context Reconfigurable Architectures (Abstract)

Rafael Maestre , Universidad Complutense, Madrid, Spain
Roman Hermida , Universidad Complutense, Madrid, Spain
Nader Bagherzadeh , University of California, Irvine, CA
Marcos Sanchez-Elez , Universidad Complutense, Madrid, Spain
Fadi Kurdahi , University of California, Irvine, CA
Milagros Fern?ndez , Universidad Complutense, Madrid, Spain
pp. 177-182

Scheduling and Partitioning for Multiple Loop Nests (Abstract)

Zhong Wang , University of Notre Dame, Notre Dame, IN
Edwin H.-M. Sha , University of Texas at Dallas, Richardson, TX
Qingfeng Zhuge , University of Texas at Dallas, Richardson, TX
pp. 183-188

Object Oriented Hardware Synthesis and Verification (Abstract)

Y. Kashai , Verisity Design, Inc., Mountain View, CA
M. Edwards , Cisco Systems, Inc., RTP, NC
T. Kuhn , Univ. of Tuebingen, Tuebingen, Germany
C. Schulz-Key , Univ. of Tuebingen, Tuebingen, Germany
T. Oppold , Univ. of Tuebingen, Tuebingen, Germany
W. Rosenstiel , Univ. of Tuebingen, Tuebingen, Germany
M. Winterholer , Univ. of Tuebingen, Tuebingen, Germany
pp. 189-194
Session 8: Special Session on Network Processors: An Industrial Perspective

System Design of a Telecommunication Router (PDF)

Richard Norman , Hyperchip, Montr?al, Qu?bec, Canada
pp. 196

Network Processing in Content Inspection Applications (Abstract)

Feliks J. Welfeld , Solidum Systems Corp., Ottawa, Ontario, Canada
pp. 197-201
Panel Discussion

Programming Models for Network Processors (PDF)

Feliks J. Welfeld , Solidum Systems, Ottawa, Canada
P. Paulin , STMicroelectronics, Ottawa, Canada
R. Norman , Hyperchip Inc., Montr?al, Canada
A. A. Jerraya , TIMA, France
pp. 202
Session 9: IP Design and Reuse

Methods for Optimizing Register Placement in Synchronous Circuits Derived Using Software Pipelining Techniques (Abstract)

Noureddine Chabini , Universit? de Montr?al, Montr?al, Qc, Canada
Yvon Savaria , Ecole Polytechnique de Montr?al, Montr?al, Qc, Canada
pp. 209-214

High-Level Automatic Pipelining for Sequential Circuits (Abstract)

Maria-Cristina V. Marinescu , Massachusetts Institute of Technology, Cambridge, MA
Martin Rinard , Massachusetts Institute of Technology, Cambridge, MA
pp. 215-220

Synthesis of Pipelined Memory Access Controllers for Streamed Data Applications on FPGA-Based Computing Engines (Abstract)

Pedro C. Diniz , University of Southern California, Marina del Rey, CA
Joonseok Park , University of Southern California, Marina del Rey, CA
pp. 221-226

Soft-Cores Generation by Instruction Set Analysis (Abstract)

Franco Fummi , Universit? di Verona, Verona, Italy
Giovanni Perbellini , Universit? di Verona, Verona, Italy
Alessandro Fin , Universit? di Verona, Verona, Italy
pp. 227-232

Concurrent-Simulation-Based Remote IP Evaluation over the Internet for System-on-a-Chip Design (Abstract)

Youn-Long Lin , National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Hung-Pin Wen , National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Chien-Yu Lin , National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
pp. 233-238

Application of Software Design Patterns to DSP Library Design (Abstract)

Pontus ?str? , Lund University, Lund, Sweden
Peter Nilsson , Lund University, Lund, Sweden
Stefan Johansson , Turin Networks, Petaluma, CA
pp. 239-243
Session 10: Formal Aspects and Distributed Systems

Accelerating Bboolean Satisfiability through Application Specific Processing (Abstract)

Ying Zhao , Princeton University, Princeton, NJ
Matthew Moskewicz , University of California at Berkeley, Berkeley, CA
Sharad Malik , Princeton University, Princeton, NJ
Conor Madigan , Massachusetts Institute of Technology, Cambridge, MA
pp. 244-249

Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems (Abstract)

Marcus T. Schmitz , University of Southampton, Southampton, United Kingdom
Bashir M. Al-Hashimi , University of Southampton, Southampton, United Kingdom
pp. 250-255

Functional Abstraction Driven Design Space Exploration of Heterogeneous Programmable Architectures (Abstract)

Prabhat Mishra , University of California, Irvine, CA
Alex Nicolau , University of California, Irvine, CA
Nikil Dutt , University of California, Irvine, CA
pp. 256-261

Modeling and Simulation of Steady State and Transient Behaviors for Emergent SoCs (Abstract)

JoAnn M. Paul , Carnegie Mellon University, Pittsburgh, PA
Donald E. Thomas , Carnegie Mellon University, Pittsburgh, PA
Arne J. Supp? , Carnegie Mellon University, Pittsburgh, PA
pp. 262-267

Control and Communication Performance Analysis of Embedded DSP Systems in the MASIC Methodology (Abstract)

Abhijit K. Deb , Royal Institute of Technology, Kista, Sweden
Axel Jantsch , Royal Institute of Technology, Kista, Sweden
Johnny ?berg , Royal Institute of Technology, Kista, Sweden
pp. 274-279
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