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System Synthesis, International Symposium on (2000)
Madrid, Spain
Sept. 20, 2000 to Sept. 22, 2000
ISSN: 1080-1820
ISBN: 0-7695-0765-4
TABLE OF CONTENTS

Reviewers (PDF)

pp. xiii
Session 1: System Level Design Research in an Industrial Setting (Invited Talks): Organizer and Chair: Don MacMillen

IP Reuse in the System on a Chip Era (Abstract)

Warren Savage , Synopsys Inc.
John Chilton , Synopsys Inc.
Raul Camposano , Synopsys Inc.
pp. 2

YAML: A Tool for Hardware Design Visualization and Capture (Abstract)

Chuck Siska , University of California at Irvine
Vivek Sinha , University of California at Irvine
Stan Liao , Synopsys Inc.
Frederic Doucet , University of California at Irvine
Rajesh Gupta , University of California at Irvine
Abhijit Ghosh , Synopsys Inc.
pp. 9
Session 2: New Frontiers for System-Level Power Management (Invited Talks): Organizer: G. De Micheli: Chair: Luca Benini

Requester-Aware Power Reduction (Abstract)

Luca Benini , Universit? di Bologna
Giovanni de Micheli , Stanford University
Yung-Hsiang Lu , Stanford University
pp. 18

Battery-Driven Dynamic Power Management of Portable Systems (Abstract)

Luca Benini , Universit? di Bologna
Enrico Macii , Politecnico di Torino
Giuliano Castelli , Politecnico di Torino
Riccardo Scarsi , Politecnico di Torino
Alberto Macii , Politecnico di Torino
pp. 25
Session 3: Code Generation and Scheduling: Chair: Bob Rau

FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors (Abstract)

Cagdas Akturan , University of Texas at Austin
Margarida F. Jacome , University of Texas at Austin
pp. 34

Instruction Scheduling for Clustered VLIW Architectures (Abstract)

Jesús Sánchez , Universitat Polit?cnica de Catalunya
Antonio González , Universitat Polit?cnica de Catalunya
pp. 41

Scheduling Coarse-Grain Operations for VLIW Processors (Abstract)

M. Bekooij , Philips Research Laboratories
A. Van der Werf , Philips Research Laboratories
N.G. Busá , Philips Research Laboratories
pp. 47

Compiler Optimization on Instruction Scheduling for Low Power (Abstract)

TingTing Hwang , National Tsing-Hua University
Chingren Lee , National Tsing-Hua University
Jenq Kuen Lee , National Tsing-Hua University
Shi-Chun Tsai , National Chi-Nan University
pp. 55
Session 4: Embedded Tutorial: Chair: Francisco Tirado
Session 6: High Level and System Level Synthesis: Chair: Petru Eles

Execution Condition Analysis in High Level Synthesis: A Unified Approach (Abstract)

J. Mendías , Universidad Complutense de Madrid
O. Peñalba , Universidad Complutense de Madrid
M.C. Molina , Universidad Complutense de Madrid
pp. 73

Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design (Abstract)

Kangnyoung Lee , Seoul National University
Hyunuk Jung , Seoul National University
Soonhoi Ha , Seoul National University
pp. 79

A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems Using a Period Graph Construct (Abstract)

Neal K. Bambha , University of Maryland at College Park
Shuvra S. Bhattacharyya , University of Maryland at College Park
pp. 91
Session 7: Reconfigurable Computing and Embedded Systems: Chair: Walid Najjar

Run-Time HW/SW Codesign for Discrete Event Systems Using Dynamically Reconfigurable Architectures (Abstract)

Rosa M. Badía , University Polit?cnica de Catalunya
Juanjo Noguera , University Aut?noma de Barcelona
pp. 100

Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization (Abstract)

Milagros Fernandez , Universidad Complutense de Madrid
Fadi J. Kurdahi , University of California at Irvine
Hartej Singh , University of California at Irvine
Nader Bagherzadeh , University of California at Irvine
Rafael Maestre , Universidad Complutense de Madrid
pp. 107
Session 8: System Level Modeling and Verification: Chair: Diederik Verkest

Intervals in Software Execution Cost Analysis (Abstract)

Fabian Wolf , Technische Universit?t Braunschweig
Rolf Ernst , Technische Universit?t Braunschweig
pp. 130

A Transformational Approach to Constraint Relaxation of a Time-Driven Simulation Model (Abstract)

Marek Jersak , Technische Universit?t Braunschweig
Rolf Ernst , Technische Universit?t Braunschweig
Dirk Ziegenbein , Technische Universit?t Braunschweig
Ying Cai , Technische Universit?t Braunschweig
pp. 137

Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator (Abstract)

C. Baumgartner , Robert Bosch GmbH
M. Meerwein , Robert Bosch GmbH
W. Glauert , University of Erlangen-Nuremberg
T. Wieja , Robert Bosch GmbH
pp. 143

Verification of Embedded Systems Using a Petri Net Based Representation (Abstract)

Luis Alejandro Cortés , Link?ping University
Zebo Peng , Link?ping University
Petru Eles , Link?ping University
pp. 149

Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripheral Cores (Abstract)

Frank Vahid , University of California at Riverside
Tony D. Givargis , University of California at Riverside
Jörg Henkel , NEC USA
pp. 163
Session 9: Embedded Tutorial: Organizer and Chair: Peter Marwedel

Code Generation for Embedded Processors (Abstract)

Rainer Leupers , University of Dortmund
pp. 173
Session 10: High-Level Power Estimation (InvitedTalks): Organizer and Chair: Donatella Sciuto

Lower Bound Estimation for Low Power High-Level Synthesis (Abstract)

Eike Schmidt , OFFIS Research Institute
Lars Kruse , OFFIS Research Institute
Gerd Jochens , OFFIS Research Institute
Ansgar Stammermann , OFFIS Research Institute
Wolfgang Nebel , OFFIS Research Institute
pp. 180

A Multi-Level Strategy for Software Power Estimation (Abstract)

C. Brandolese , Politecnico di Milano
F. Salice , Politecnico di Milano
W. Fornaciari , Politecnico di Milano
L. Pomante , Politecnico di Milano
D. Sciuto , Politecnico di Milano
pp. 187

Source Code Optimization and Profiling of Energy Consumption in Embedded Systems (Abstract)

Tajana ?imunic , Stanford University
Luca Benini , University of Bologna
Mat Hans , HP Labs
Giovanni de Micheli , Stanford University
pp. 193
Session 11: System Design Methodologies and Experiences: Chair: Nikil Dutt

Mapping Array Communication onto FIFO Communication - Towards an Implementation (Abstract)

Jeffrey Kang , Philips Research Laboratories
Paul Lippens , Philips Research Laboratories
Albert Van der Werf , Philips Research Laboratories
pp. 207

Hardware Synthesis from SPDF Representation for Multimedia Applications (Abstract)

Chanik Park , Seoul National University
Soonhoi Ha , Seoul National University
pp. 215

Experiments with the Peripheral Virtual Component Interface (Abstract)

Frank Vahid , University of California at Riverside and University of California at Irvine
Roman L. Lysecky , University of California at Riverside
Tony D. Givargis , University of California at Riverside
pp. 221

Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation (Abstract)

Antonio Mocholí , Universidad Politecnica de Valencia
Joaquín Cerdá , Universidad Politecnica de Valencia
Franciso Ballester , Universidad Politecnica de Valencia
Rafael Gadea , Universidad Politecnica de Valencia
pp. 225

Index of Authors (PDF)

pp. 231
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