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System Synthesis, International Symposium on (1997)
Antwerp, BELGIUM
Sept. 17, 1997 to Sept. 19, 1997
ISSN: 1080-1820
ISBN: 0-8186-7949-2

Reviewers (PDF)

pp. x
Session 1: Formal Specification and Validation

Quick conservative causality analysis (Abstract)

E.M. Sentovich , Cadence Berkeley Lab., CA, USA
pp. 2

An Efficient Representation for Formal Synthesis (Abstract)

Christian Blumenroehr , Universitaet Karlsruhe
Dirk Eisenbiegler , Universitaet Karlsruhe
pp. 9
Session 2: Fast Prototyping and Code Generation

Prototyping of the Receiver Unit for a Broadband Access Network (Abstract)

A. Hein , ESAT/ACCA Laboratory
J. Dalcolmo , ESAT/ACCA Laboratory
P. Le Corre , ESAT/ACCA Laboratory
R. Lauwereins , ESAT/ACCA Laboratory
M. Ade' , ESAT/ACCA Laboratory
pp. 26

Constraint Analysis for DSP Code Generation (Abstract)

Bart Mesman , Philips Research laboratories
Marino T.J. Strik , Philips Research laboratories
Adwin H. Timmer , Philips Research laboratories
Jef L. Van Meerbergen , Philips Research laboratories
Jochen A.G. Jess , Design Automation Section Eindhoven University of Technology
pp. 33
Session 3: Novel Compilation and Optimization Issues

Reducing the complexity of ILP formulations for synthesis (Abstract)

Anne Mignotte , Laboratoire de l'Informatique du Parall?lisme
Olivier Peyran , Laboratoire de l'Informatique du Parall?lisme
pp. 58
Session 4: Memory Management Issues

Architectural Exploration and Optimization of Local Memory in Embedded Systems (Abstract)

Preeti Ranjan Panda , University of California, Irvine
Nikil D. Dutt , University of California, Irvine
Alexandru Nicolau , University of California, Irvine
pp. 90
Session 5: System-Level Synthesis and Design

Optimization Method for Broadband FIR Filter Design using Common Subexpressions Elimination (Abstract)

Robert Pasko , IMEC Leuven, Belgium
Patrick Schaumont , IMEC Leuven, Belgium
Veerle Derudder , IMEC Leuven, Belgium
Daniela Durackova , IMEC Leuven, Belgium
pp. 100

A Scheduling and Pipelining Algorithm for Hardware/Software Systems (Abstract)

Smita Bakshi , University of California, Irvine
Daniel D. Gajski , University of California, Irvine
pp. 113
Session 6: HW/SW Specification and Debugging

Co-Emulation and Debugging of HW/SW-Systems (Abstract)

Gernot Koch , Forschungszentrum Informatik
Udo Kebschull , Forschungszentrum Informatik
Wolfgang Rosenstiel , University of Tuebingen
pp. 120

A Source-level Dynamic Analysis Methodology and Tool for High-level Synthesis (Abstract)

Chih-Tung Chen , Unified Design System Laboratory Motorola, Inc.
Kayhan Kucukcakar , Unified Design System Laboratory Motorola, Inc.
pp. 134

Author Index (PDF)

pp. 141
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