The Community for Technology Leaders
System Synthesis, International Symposium on (1995)
Cannes, France
Sept. 13, 1995 to Sept. 15, 1995
ISBN: 0-8186-7076-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Session 1: Hardware/Software Co-Design

Sensitivity-driven co-synthesis of distributed embedded systems (Abstract)

T.-Y. Yen , Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 0004

Multiple-process behavioral synthesis for mixed hardware-software systems (Abstract)

J.K. Adams , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0010

An approach to interface synthesis (Abstract)

J. Madsen , Dept. of Comput. Sci., Tech. Univ. Denmark, Lyngby, Denmark
B. Hald , Dept. of Comput. Sci., Tech. Univ. Denmark, Lyngby, Denmark
pp. 0016

The Chinook hardware/software co-synthesis system (Abstract)

P.H. Chou , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
R.B. Ortega , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 0022

Clustering for improved system-level functional partitioning (Abstract)

F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
D.D. Gajski , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 0028
Session 2: Code Generation and Software Synthesis

Optimal code generation for embedded memory non-homogeneous register architectures (Abstract)

G. Araujo , Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 0036

Optimal register assignment to loops for embedded code generation (Abstract)

D.J. Kolson , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
K. Kennedy , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 0042

Real-time multi-tasking in software synthesis for information processing systems (Abstract)

F. Thoen , IMEC, Leuven, Belgium
M. Cornero , IMEC, Leuven, Belgium
G. Goossens , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 0048

Time-constrained code compaction for DSPs (Abstract)

R. Leupers , Dept. of Comput. Sci., Dortmund Univ., Germany
P. Marwedel , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 0054

Industrial experience using rule-driven retargetable code generation for multimedia applications (Abstract)

C. Liem , Inst. Nat. Polytech. de Grenoble, France
P. Paulin , Inst. Nat. Polytech. de Grenoble, France
M. Cornero , Inst. Nat. Polytech. de Grenoble, France
A. Jerraya , Inst. Nat. Polytech. de Grenoble, France
pp. 0060
Session 3: Behavioral Synthesis

Synthesis of pipelined DSP accelerators with dynamic scheduling (Abstract)

P. Schaumont , IMEC, Leuven, Belgium
B. Vanthournout , IMEC, Leuven, Belgium
I. Bolsens , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 0072

An exact methodology for scheduling in a 3D design space (Abstract)

S. Chaudhuri , Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
S.A. Blythe , Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
R.A. Walker , Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 0078

Procedure exlining: a transformation for improved system and behavioral synthesis (Abstract)

F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 0084

Array mapping in behavioral synthesis (Abstract)

H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.E. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0090

On the use of VHDL-based behavioral synthesis for telecom ASIC design (Abstract)

M. Genoe , Alcatel Bell Telephone, Antwerp, Belgium
P. Vanoostende , Alcatel Bell Telephone, Antwerp, Belgium
G. Van Wauwe , Alcatel Bell Telephone, Antwerp, Belgium
pp. 0096
Session 4: Low Power and Estimation Techniques for Behavioral and System Level Synthesis

Scheduling and resource binding for low power (Abstract)

E. Musoll , Dept. of Comput. Architecture, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Cortadella , Dept. of Comput. Architecture, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 0104

Power analysis and low-power scheduling techniques for embedded DSP software (Abstract)

M.T.-C. Lee , Fujitsu Labs. of America, San Jose, CA, USA
V. Tiwari , Fujitsu Labs. of America, San Jose, CA, USA
S. Malik , Fujitsu Labs. of America, San Jose, CA, USA
M. Fujita , Fujitsu Labs. of America, San Jose, CA, USA
pp. 0110

A path-based technique for estimating hardware runtime in HW/SW-cosynthesis (Abstract)

J. Henkel , Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
R. Ernst , Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
pp. 0116

A comprehensive estimation technique for high-level synthesis (Abstract)

S.Y. Ohm , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
F.J. Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
N. Dutt , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
M. Xu , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 0122

Profiling in the ASP codesign environment (Abstract)

M.F. Parkinson , Dept. of Electr. & Comput. Eng., Queensland Univ., St. Lucia, Qld., Australia
S. Parameswaran , Dept. of Electr. & Comput. Eng., Queensland Univ., St. Lucia, Qld., Australia
pp. 0128
Session 5: Design Methods for HW/SW Systems

WWW based structuring of codesigns (Abstract)

P.G. Ploger , GMD-SET, Sankt Augustin, Germany
J. Wilberg , GMD-SET, Sankt Augustin, Germany
M. Langevin , GMD-SET, Sankt Augustin, Germany
R. Camposano , GMD-SET, Sankt Augustin, Germany
pp. 0138

System level verification of video and image processing specifications (Abstract)

H. Samsom , IMEC, Leuven, Belgium
F. Franssen , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 0144

Synthesis of system-level communication by an allocation-based approach (Abstract)

J.-M. Daveau , TIMA INPG Lab., Grenoble, France
T.B. Ismail , TIMA INPG Lab., Grenoble, France
A.A. Jerraya , TIMA INPG Lab., Grenoble, France
pp. 0150

Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model (Abstract)

J. Teich , Comput. Eng. & Comm. Networks Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
L. Thiele , Comput. Eng. & Comm. Networks Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
E.A. Lee , Comput. Eng. & Comm. Networks Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
pp. 0156

A system level design methodology for the optimization of heterogeneous multiprocessors (Abstract)

M. Schwiegershausen , Lab. fur Informationstechnologie, Hannover Univ., Germany
P. Pirsch , Lab. fur Informationstechnologie, Hannover Univ., Germany
pp. 0162
Benchmarking

1995 high level synthesis design repository (Abstract)

P.R. Panda , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N.D. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 0170

Author Index (PDF)

pp. 0175
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