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Quality Electronic Design, International Symposium on (2009)
San Jose, CA, USA
Mar. 16, 2009 to Mar. 18, 2009
ISBN: 978-1-4244-2952-3
pp: 442-446
Akif Sultan , Advanced Micro Devices, Inc., Texas, USA
John Faricelli , Advanced Micro Devices, Inc., Texas, USA
Sushant Suryagandh , Advanced Micro Devices, Inc., Texas, USA
Hans vanMeer , Advanced Micro Devices, Inc., Texas, USA
Kaveri Mathur , Advanced Micro Devices, Inc., Texas, USA
James Pattison , Advanced Micro Devices, Inc., Texas, USA
Sean Hannon , Advanced Micro Devices, Inc., Texas, USA
Greg Constant , Advanced Micro Devices, Inc., Texas, USA
Kalyana Kumar , Advanced Micro Devices, Inc., Texas, USA
Kevin Carrejo , Advanced Micro Devices, Inc., Texas, USA
Joe Meier , Advanced Micro Devices, Inc., Texas, USA
Rasit O. Topaloglu , Advanced Micro Devices, Inc., Texas, USA
Darin Chan , Advanced Micro Devices, Inc., Texas, USA
Uwe Hahn , Advanced Micro Devices, Inc., Texas, USA
Thorsten Knopp , Advanced Micro Devices, Inc., Texas, USA
Victor Andrade , Advanced Micro Devices, Inc., Texas, USA
Bill Gardiol , Advanced Micro Devices, Inc., Texas, USA
Steve Hejl , Advanced Micro Devices, Inc., Texas, USA
David Wu , Advanced Micro Devices, Inc., Texas, USA
James Buller , Advanced Micro Devices, Inc., Texas, USA
Larry Bair , Advanced Micro Devices, Inc., Texas, USA
Ali Icel , Advanced Micro Devices, Inc., Texas, USA
Yuri Apanovich , Advanced Micro Devices, Inc., Texas, USA
ABSTRACT
Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, - CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layout-dependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.
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CITATION

K. Kumar et al., "CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design," Quality Electronic Design, International Symposium on(ISQED), San Jose, CA, USA, 2009, pp. 442-446.
doi:10.1109/ISQED.2009.4810335
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