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Quality Electronic Design, International Symposium on (2009)
San Jose, CA, USA
Mar. 16, 2009 to Mar. 18, 2009
ISBN: 978-1-4244-2952-3
pp: 13-18
Balaji Vaidyanathan , Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
Anthony S. Oates , Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State University, USA
Yu Wang , Department of Electronics Engineering, Tsinghua University, Beijing, China
ABSTRACT
This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread.
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CITATION

A. S. Oates, B. Vaidyanathan, Yuan Xie and Yu Wang, "NBTI-aware statistical circuit delay assessment," Quality Electronic Design, International Symposium on(ISQED), San Jose, CA, USA, 2009, pp. 13-18.
doi:10.1109/ISQED.2009.4810263
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