Quality Electronic Design, International Symposium on (2008)
Mar. 17, 2008 to Mar. 19, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.17
This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.
D. Ganesan, J. Wang, Y. Cao and A. Mitev, "Finite-Point Gate Model for Fast Timing and Power Analysis," 2008 9th International Symposium on Quality Electronic Design (ISQED '08)(ISQED), San Jose, CA, 2008, pp. 657-662.