The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2007)
San Jose, California
Mar. 26, 2007 to Mar. 28, 2007
ISBN: 0-7695-2795-7
TABLE OF CONTENTS
Participating Organizations
Introduction

Welcome Notes (PDF)

pp. xvii-xviii

Advisory Committee (PDF)

pp. xxiii
Tutorials

Tutorial I (PDF)

pp. null

Tutorial II (PDF)

pp. null
Evening Panel Discussion EP1

DFM--EDA's Salvation or its Excuse for Being out of Touch with Engineering? (PDF)

Robbert Dobkins , CTO, Linear Technologies
Mike Smayling , CTO Applied Materials
Ivan Pesic , Silvaco/Simucad
Joe Sawicki , VP Design to Silicon Div Mentor Graphics
Pallab Chatterjee , SiliconMap
Resve Saleh , ECE Dept UBC Vancouver
pp. 7-8
Plenary Session 1P
Session 1A: Design for Manufacturing

Variation (Abstract)

Hayden Taylor , MIT, USA
Xiaolin Xie , MIT, USA
Daniel Truque , MIT, USA
Ajay Somani , MIT, USA
Ali Farahanchi , MIT, USA
Daihyun Lim , MIT, USA
Hong Cai , MIT, USA
Karen Gettings , MIT, USA
Duane Boning , MIT, USA
Nigel Drego , MIT, USA
pp. 15-20

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation (Abstract)

Noriaki Nakayama , Tokyo Institute of Technology, Japan
Takashi Sato , Tokyo Institute of Technology, Japan
Kazuya Masu , Tokyo Institute of Technology, Japan
Shuhei Amakawa , Tokyo Institute of Technology, Japan
Takumi Uezono , Tokyo Institute of Technology, Japan
Shiho Hagiwara , Tokyo Institute of Technology, Japan
Kenichi Okada , Tokyo Institute of Technology, Japan
pp. 21-26

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS (Abstract)

Rajani Kuchipudi , San Francisco State University, USA
Hamid Mahmoodi , San Francisco State University, USA
pp. 27-32

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs (Abstract)

Rouwaida Kanj , IBM Austin Research Labs, USA
Sani Nassif , IBM Austin Research Labs, USA
Jayakumaran Sivagnaname , IBM Austin Research Labs, USA
Rajiv Joshi , IBM TJ Watson Labs, USA
Tuyet Nguyen , IBM Austin Research Labs, USA
JB Kuang , IBM Austin Research Labs, USA
Chandler McDowell , IBM Austin Research Labs, USA
Dhruva Acharyya , IBM Austin Research Labs, USA
pp. 33-40
Session 1B: Device and Circuit Reliability

A New Simulation Method for NBTI Analysis in SPICE Environment (Abstract)

Alex Gyure , Synopsys Inc, USA
Rakesh Vattikonda , Arizona State University, USA
Yansheng Luo , Synopsys Inc, USA
Sam Lo , Synopsys Inc, USA
Yu Cao , Arizona State University, USA
Dino Toffolon , Synopsys Inc, USA
Kishore Singhal , Synopsys Inc, USA
Xiaoning Qi , Synopsys Inc, USA
Mahmoud Shahram , Synopsys Inc, USA
pp. 41-46

Combating NBTI Degradation via Gate Sizing (Abstract)

Xiangning Yang , University of Wisconsin-Madison, USA
Kewal Saluja , University of Wisconsin-Madison, USA
pp. 47-52

Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability (Abstract)

Benoit Dubois , Institut d'Electronique du Solide et des Systemes, France
Luc Hebrard , Institut d'Electronique du Solide et des Systemes, France
Francis Braun , Institut d'Electronique du Solide et des Systemes, France
Jean-Baptiste Kammerer , Institut d'Electronique du Solide et des Systemes, France
pp. 53-58

A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays (Abstract)

Man Young Sung , Korea University, Korea
Seung Woo Yu , Korea University, Korea
Sang Jun Hwang , Korea University, Korea
Aram Shin , Korea University, Korea
pp. 59-66
Session 1C: Power and Thermal Management

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers (Abstract)

Greg Link , York College of Pennsylvania
Sami Kirolos , Rice University
Tamer Ragheb , Rice University
Andrew Ricketts , Pennsylvania State University, USA
Vijaykrishnan Narayanan , Pennsylvania State University
Yehia Massoud , Rice University
Mosin Mondal , Rice University
pp. 67-72

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew (Abstract)

Sherif A. Tawfik , University of Wisconsin-Madison, USA
Volkan Kursun , University of Wisconsin-Madison, USA
pp. 73-78

Speculative Energy Scheduling for LDPC Decoding (Abstract)

Gwan Choi , Texas A&M University, USA
Weihuang Wang , Texas A&M University, USA
pp. 79-84

Dynamic Power Management by Combination of Dual Static Supply Voltages (Abstract)

Kevin Nowka , IBM Corporation, USA
Kanak Agarwal , IBM Corporation, USA
pp. 85-92
Session 1D: Analog and Mixed Signal Design

Low Voltage Buffered Bandgap Reference (Abstract)

Donald S. Gardner , Intel Corporation, USA
Gerhard Schrom , Intel Corporation, USA
Sung Tae Moon , Intel Corporation, USA
Kenneth Ikeda , Intel Corporation, USA
Gell Gellman , Intel Corporation, USA
Tanay Karnik , Intel Corporation, USA
David J. Rennie , University of Waterloo, Canada
Peter Hazucha , Intel Corporation, USA
Fabrice Paillet , Intel Corporation, USA
pp. 93-97

A DLL Based Multiphase Hysteretic DC-DC Converter (Abstract)

Rizwan Bashirullah , Member, IEEE; University of Florida, USA
Pengfei Li , Student Member, IEEE; University of Florida, USA
pp. 98-101

Statistical Timing Analysis Considering Spatial Correlations (Abstract)

Venkataramanan Balakrishnan , Purdue University, USA
Cheng-Kok Koh , Purdue University, USA
Yiran Chen , Synopsys Inc., USA
Hong Li , Purdue University, USA
pp. 102-107

Systematic Design of a Flash ADC for UWB Applications (Abstract)

E. Martin I. Gustafsson , Royal Institute of Technology, Sweden
Ana Rusu , Royal Institute of Technology, Sweden
Liang Rong , Royal Institute of Technology, Sweden
Mohammed Ismail , Royal Institute of Technology, Sweden
pp. 108-114
Luncheon Speech
Session 2A: Quality and Reliability

FinFET Based SRAM Design for Low Standby Power Applications (Abstract)

Kaushik Roy , Purdue University, USA
Keejong Kim , Purdue University, USA
Tamer Cakici , Purdue University, USA
pp. 127-132

Compact Modeling of a PD SOI MESFET for Wide Temperature Designs (Abstract)

Yu Cao , Arizona State University, USA
Trevor Thornton , Arizona State University, USA
Joseph Ervin , Arizona State University, USA
Asha Balijepalli , Arizona State University, USA
pp. 133-138

Modeling of PMOS NBTI Effect Considering Temperature Variation (Abstract)

Yu Wang , Tsinghua Univ., China
Yuan Xie , Pennsylvania State University, USA
Hong Luo , Tsinghua Univ., China
Ku He , Tsinghua Univ., China
Rong Luo , Tsinghua Univ., China
Huazhong Yang , Tsinghua Univ., China
pp. 139-144

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI (Abstract)

Ching-Te Chuang , IBM T.J. Watson Research Center, USA
Jie Deng , Stanford University, USA
Keunwoo Kim , IBM T.J. Watson Research Center, USA
H.-S Philip Wong , Stanford University, USA
pp. 145-152
Session 2B: Advances in Timing and Power in Physical Design

A Low-Power Multi-Pin Maze Routing Methodology (Abstract)

Mohamed Elmasry , University of Waterloo, Canada
Tor Myklebust , University of Waterloo, Canada
Ahmed Youssef , University of Waterloo, Canada
Mohab Anis , University of Waterloo, Canada
pp. 153-158

Design and Analysis of "Tree+Local Meshes" Clock Architecture (Abstract)

Rajeev Murgai , Fujitsu Laboratories of America, Inc., USA
Gustavo R. Wilke , Fujitsu Laboratories of America, Inc., USA
pp. 165-170

An Efficient Algorithm for RLC Buffer Insertion (Abstract)

Zhanyuan Jiang , Texas A&M University, USA
Jiang Hu , Texas A&M University, USA
Weiping Shi , Texas A&M University, USA
Shiyan Hu , Texas A&M University, USA
pp. 171-175

Fast Crosstalk Repair by Quick Timing Change Estimation (Abstract)

Nahmsuk Oh , Synopsys, Inc., USA
Alireza Kasnavi , Synopsys, Inc., USA
Peivand Tehrani , Synopsys, Inc., USA
pp. 176-184
Session 2C: Power-Aware System Design Methodologies

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays (Abstract)

Minh Q. Do , Chalmers University of Technology, Sweden
Lars Bengtsson , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
Mindaugas Drazdziulis , Chalmers University of Technology, Sweden
pp. 185-191

Cross Layer Error Exploitation for Aggressive Voltage Scaling (Abstract)

Ahmed M. Eltawil , UC Irvine, USA
Rouwaida Kanj , IBM Austin Research Labs, USA
Amin Khajeh Djahromi , UC Irvine, USA
Fadi J. Kurdahi , UC Irvine, USA
pp. 192-197

A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems (Abstract)

Hwisung Jung , University of Southern California, USA
Massoud Pedram , University of Southern California, USA
pp. 198-203

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems (Abstract)

Huazhong Yang , Tsinghua University, China
Hui Wang , Tsinghua University, China
Li Shang , Queen's University, Canada
Robert P. Dick , Northwestern University, USA
Yongpan Liu , Tsinghua University, China
pp. 204-209

A Unified Optimal Voltage Selection Methodology for Low-Power Systems (Abstract)

Ani Nahapetian , University of California Los Angeles, USA
Roozbeh Jafari , University of Texas at Dallas, USA
Majid Sarrafzadeh , University of California Los Angeles, USA
Foad Dabiri , University of California Los Angeles, USA
pp. 210-218
Session 2D: Poster Papers

Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion (Abstract)

Charbel J. Akl , University of Louisiana at Lafayette, USA
Magdy A. Bayoumi , University of Louisiana at Lafayette, USA
pp. 219-224

A 8b 10Ms/s Low Power Pipelined A/D Converter (Abstract)

Bi Yuan , San Jose State University, USA
Lili He , San Jose State University, USA
Yi Zhang , San Jose State University, USA
pp. 225-228

First-Order Continuous-Time Sigma-Delta Modulator (Abstract)

Lili He , San Jose State University, USA
Yamei Li , San Jose State University, USA
pp. 229-232

Reducing EPL Alignment Errors for Large VLSI Layouts (Abstract)

Prosenjit Gupta , International Institute of Information Technology, India
Yokesh Kumar , International Institute of Information Technology, India
pp. 233-238

Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS (Abstract)

Zhiyu Liu , University of Wisconsin-Madison, USA
Volkan Kursun , University of Wisconsin-Madison, USA
pp. 239-244

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals (Abstract)

Chung-Kuan Cheng , University of California, San Diego, USA
Ling Zhang , University of California, San Diego, USA
Kevin Hamilton , Qualcomm Inc., USA
Hongyu Chen , Synopsys Inc., USA
Bo Yao , Mentorgraphics Corp., USA
pp. 251-256
Session 2D: Poster Papers

Tests on Symmetry and Continuity between BSIM4 and BSIM5 (Abstract)

Wei Bian , Peking University, China
Yu Chen , Peking University, China
Bo Li , Peking University, China
Feng Liu , Peking University, China
Xudong Niu , Peking University, China
Yadong Tao , Peking University, China
Frank He , Peking University, China
Jinhua Hu , Peking University, China
Yan Song , Peking University, China
pp. 263-268

Interface Specification Assurance Methods (Abstract)

Taoyong Ni , East China Normal University, China
Naiyong Jin , East China Normal University, China
pp. 269-274

Multi-Dimensional Circuit and Micro-Architecture Level Optimization (Abstract)

Zhenyu (Jerry) Qi , University of Virginia, USA
Matthew Ziegler , IBM, T.J. Watson Research Center, USA
Mircea R. Stan , University of Virginia, USA
Jan M. Rabaey , University of California at Berkeley, USA
Stephen V. Kosonocky , IBM, T.J. Watson Research Center, USA
pp. 275-280

Processing High Volume Scan Test Results for Yield Learning (Abstract)

Phil Burlison , Inovys Corp.
Alfred L. Crouch , Inovys Corp.
Dennis Ciplickas , PDF Solutions, Inc.
pp. 293-298

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture (Abstract)

Bing Lu , Cadence Design Sys. Inc, USA
Weixiang Shen , Tsinghua University, China
Jiang Hu , Texas A&M University, USA
Yici Cai , Tsinghua University, China
Xianlong Hong , Tsinghua University, China
pp. 299-304

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits (Abstract)

David Rennie , University of Waterloo, Canada
Manoj Sachdev , University of Waterloo, Canada
pp. 305-310

Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays (Abstract)

Daniela De Venuto , DEE Politecnico di Bari, Italy
Bruno Ricco , DEIS Universita di Bologna, Italy
pp. 311-316

Fine-Grained Redundancy in Adders (Abstract)

Dinesh Somesekhar , Intel Corporation, USA
Kaushik Roy , Purdue University, USA
Patrick Ndai , Purdue University, USA
Shih-Lien Lu , Intel Corporation, USA
pp. 317-321

MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks (Abstract)

A. Ilumoka , University of Hartford, USA
Hong Lang Tan , University of Hartford, USA
pp. 322-326

Variation Aware Timing Based Placement Using Fuzzy Programming (Abstract)

N. Ranganathan , University of South Florida, USA
V. Mahalingam , University of South Florida, USA
pp. 327-332

Variation Analysis of CAM Cells (Abstract)

Amol Mupid , The Pennsylvania State University, USA
Y. Xie , The Pennsylvania State University, USA
N. Vijaykrishnan , The Pennsylvania State University, USA
M.J. Irwin , The Pennsylvania State University, USA
Madhu Mutyam , International Institute of Information Technology, India
pp. 333-338

Design-for-Manufacture for Multi Gate Oxide CMOS Process (Abstract)

Xin Wu , Xilinx Inc., USA
Jenny Fan , Xilinx Inc., USA
Mei Ma , Xilinx Inc., USA
Richard Li , Xilinx Inc., USA
Tony Vo , Xilinx Inc., USA
Xiao-Yu Li , Xilinx Inc., USA
Qi Lin , Xilinx Inc., USA
pp. 339-343

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure (Abstract)

Shih-Chieh Chang , National Tsing Hua University, Taiwan
Cheng-Hung Lin , National Tsing Hua University, Taiwan
Yu-Min Kuo , National Tsing Hua University, Taiwan
Pei-Hsin Ho , Synopsys, Inc.
Chun-Yao Wang , National Tsing Hua University, Taiwan
pp. 344-349

Power Delivery Aware Floorplanning for Voltage Island Designs (Abstract)

Yici Cai , Tsinghua University, China
Bin Liu , Tsinghua University, China
Xianlong Hong , Tsinghua University, China
Qiang Zhou , Tsinghua University, China
Jin Shi , Tsinghua University, China
pp. 350-355

Passive Modeling of Interconnects by Waveform Shaping (Abstract)

Bruce McGaughy , Cadence Design Systems Inc., USA
Sheldon X.-D. Tan , University of California, Riverside, USA
Boyuan Yan , University of California, Riverside, USA
Pu Liu , University of California, Riverside, USA
pp. 356-361

A Power Network Synthesis Method for Industrial Power Gating Designs (Abstract)

Zhian Lin , Synopsys Inc., USA
Kaijian Shi , Synopsys (Professional Services), USA
Yi-Min Jiang , Synopsys Inc., USA
pp. 362-367

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint (Abstract)

Sudhakar M. Reddy , University of Iowa, USA
Yuan Cai , University of Iowa, USA
Bashir M. Al-Hashimi , University of Southampton, UK
pp. 368-373

Challenges in Evaluations for a Typical-Case Design Methodology (Abstract)

Yuji Kunitake , Kyushu Institute of Technology, Japan
Toshinori Sato , Kyushu University, Japan
Akihiro Chiyonobu , Kyushu Institute of Technology, Japan
Koichiro Tanaka , Kyushu Institute of Technology, Japan
pp. 374-379

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs (Abstract)

Hamid R. Zarandi , Sharif University of Technology; Bristol University, UK
Dhiraj K. Pradhan , Bristol University, UK
Seyed G. Miremadi , Sharif University of Technology
Jimson Mathew , Bristol University, UK
pp. 380-385

Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors (Abstract)

Xiaofang Wang , Villanova University, USA
Sotirios G. Ziavras , New Jersey Institute of Technology, USA
pp. 386-391

A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating (Abstract)

Santosh Kumar Panigrahi , Pulsecore Semiconductor (India) Pvt. Ltd., India
Gautam Kumar Singh , Pulsecore Semiconductor (India) Pvt. Ltd., India
pp. 392-397

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis (Abstract)

Joon-Sung Yang , University of Texas, USA
Anand Rajaram , University of Texas, USA; Texas Instruments Inc., USA
Jian Chen , University of Texas, USA
Ninghy Shi , University of Texas, USA
David Z. Pan , University of Texas, USA
pp. 398-403

Built-In Test of RF Mixers Using RF Amplitude Detectors (Abstract)

Chaoming Zhang , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
Ranjit Gharpurey , The University of Texas at Austin, USA
pp. 404-409

Glitch Control with Dynamic Receiver Threshold Adjustment (Abstract)

Spyros Tragoudas , Southern Illinois University at Carbondale, USA
Haibo Wang , Southern Illinois University at Carbondale, USA
Michael N. Skoufis , Southern Illinois University at Carbondale, USA
Themistoklis Haniotakis , Southern Illinois University at Carbondale, USA
pp. 410-415

Programmable High Speed Multi-Level Simultaneous Bidirectional I/O (Abstract)

Yong Sin Kim , Univ. of California, Santa Cruz, USA
Sung-Mo Kang , Univ. of California, Santa Cruz, USA
pp. 416-419

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations (Abstract)

Spyros Tragoudas , Southern Illinois University Carbondale, USA
Manoj Kumar Goparaju , Southern Illinois University Carbondale, USA
pp. 420-425

Energy-Minimization Model for Fill Synthesis (Abstract)

Rasit Onur Topaloglu , University of California San Diego, USA
pp. 444-451

On-Chip Inductance in X Architecture Enabled Design (Abstract)

Li Song , Cadence Design Systems, Inc., USA
Narain D. Arora , Cadence Design Systems, Inc., USA
Santosh Shah , Cadence Design Systems, Inc., USA
Arani Sinha , Cadence Design Systems, Inc., USA
pp. 452-457

Impact of Variability on Clock Skew in H-tree Clock Networks (Abstract)

Ramalingam Sridhar , University of Buffalo (SUNY), USA
Ashok Narasimhan , University of Buffalo (SUNY), USA
pp. 458-466
Session 3A: Electrical Quality

A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances (Abstract)

Andrew B. Kahng , University of California at San Diego, USA
Rasit Onur Topaloglu , University of California at San Diego, USA
pp. 467-474

SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design (Abstract)

Moon-Hyun Yoo , Samsung Electronics, Korea
Jeong-Taek Kong , Samsung Electronics, Korea
Jong-Bae Lee , Samsung Electronics, Korea
Ho-Soon Shin , Samsung Electronics, Korea
Jeong-Yeol Kim , Samsung Electronics, Korea
pp. 475-480

Pareto-Front Computation and Automatic Sizing of CPPLLs (Abstract)

Ulf Schlichtmann , Techn. Univ. Muenchen, Germany
Helmut Graeb , Techn. Univ. Muenchen, Germany
Jun Zou , Techn. Univ. Muenchen, Germany
Daniel Mueller , Techn. Univ. Muenchen, Germany
pp. 481-486

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization (Abstract)

Igor L. Markov , University of Michigan at Ann Arbor, USA
Valeria Bertacco , University of Michigan at Ann Arbor, USA
Kai-hui Chang , University of Michigan at Ann Arbor, USA
David A. Papa , University of Michigan at Ann Arbor, USA
pp. 487-494
Session 3B: Analog and RF Testing

Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model (Abstract)

Jacob A. Abraham , The University of Texas at Austin, USA
Joonsung Park , The University of Texas at Austin, USA
Hongjoong Shin , The University of Texas at Austin, USA
pp. 495-500

Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications (Abstract)

Sai Durbha , Southern Illinois University, USA
Rui Xiao , Southern Illinois University, USA
Haibo Wang , Southern Illinois University, USA
Amit Laknaur , Southern Illinois University, USA
pp. 501-506

Achieving Low-Cost Linearity Test and Diagnosis of \Sigma \Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling (Abstract)

Peng Li , Texas A&M University, USA
Wei Dong , Texas A&M University, USA
Guo Yu , Texas A&M University, USA
pp. 513-518

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's (Abstract)

Leonardo Reyneri , Politecnico di Torino, Italy
Daniela De Venuto , Politecnico di Bari, Italy
pp. 519-526
Session 3C: Low Power Circuits

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM (Abstract)

Toshinori Sato , Kyushu University, Japan
Yuji Kunitake , Kyushu Institute of Technology, Japan
pp. 539-544

A High Performance, Scalable Multiplexed Keeper Technique (Abstract)

Kaushik Roy , Purdue University, USA
Jaydeep P. Kulkarni , Purdue University, USA
pp. 545-549

On-Line Adjustable Buffering for Runtime Power Reduction (Abstract)

Sherief Reda , Brown University, USA
Puneet Sharma , UC San Diego, USA
Andrew B. Kahng , UC San Diego, USA
pp. 550-555
Plenary Session 2P
Session 4A: Package Circuit Co-Design

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design (Abstract)

Jungtae Lee , Samsung Electronics, Co., Ltd., Korea
Eunseok Song , Samsung Electronics, Co., Ltd., Korea
Sa-Yoon Kang , Samsung Electronics, Co., Ltd., Korea
Woojin Jin , Samsung Electronics, Co., Ltd., Korea
Kiwon Choi , Samsung Electronics, Co., Ltd., Korea
Heeseok Lee , Samsung Electronics, Co., Ltd., Korea
pp. 573-579

Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology (Abstract)

Robert E. Jones , Freescale Semiconductor Inc., USA
Ritwik Chatterjee , Freescale Semiconductor Inc., USA
Shahid Rauf , Freescale Semiconductor Inc., USA
Syed M. Alam , Freescale Semiconductor Inc., USA
pp. 580-585

A Design Methodology for Matching Improvement in Bandgap References (Abstract)

Hamilton Klimach , Federal University of Rio Grande do Sul, Brazil
Juan Pablo Martinez Brito , Federal University of Rio Grande do Sul, Brazil
Sergio Bampi , Federal University of Rio Grande do Sul, Brazil
pp. 586-594
Session 4B: High Level Optimization

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs (Abstract)

David C. Zaretsky , University of Illinois at Chicago, USA
Gaurav Mittal , University of Illinois at Chicago, USA
Robert P. Dick , Northwestern University, USA
Prith Banerjee , University of Illinois at Chicago, USA
pp. 595-601

Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis (Abstract)

Jian-Cheng Lin , National Tsing Hua University, Taiwan
Cheng-Tao Hsieh , National Tsing Hua University, Taiwan
Shih-Chieh Chang , National Tsing Hua University, Taiwan
pp. 602-606

Transistor-Level Synthesis for Low-Power Applications (Abstract)

Dimitri Kagaris , Southern Illinois University, USA
Themistoklis Haniotakis , Southern Illinois University, USA
pp. 607-612

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis (Abstract)

Zeljko Zilic , McGill University, Canada
Jean-Samuel Chenard , McGill University, Canada
Marc Boule , McGill University, Canada
pp. 613-620
Session 4C: Interconnects and Power Grids

Self-Time Regenerators for High-Speed and Low-Power Interconnect (Abstract)

David Blaauw , University of Michigan, Ann Arbor, USA
Prashant Singh , University of Michigan, Ann Arbor, USA
Jae-sun Seo , University of Michigan, Ann Arbor, USA
Dennis Sylvester , University of Michigan, Ann Arbor, USA
pp. 621-626

Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization (Abstract)

Hong Li , Purdue University, USA
Cheng-Kok Koh , Purdue University, USA
Venkataramanan Balakrishnan , Purdue University, USA
Jitesh Jain , Purdue University, USA
pp. 627-632

General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits (Abstract)

Hao Yu , University of California, Los Angeles, USA
Sheldon X.-D. Tan , University of California, Riverside, USA
Boyuan Yan , University of California, Riverside, USA
Jeffrey Fan , University of California, Riverside, USA
Ning Mi , University of California, Riverside, USA
pp. 633-638

Investigating Crosstalk in Sub-Threshold Circuits (Abstract)

David Blaauw , University of Michigan, Ann Arbor, USA
Mini Nanua , Sun Microsystems Inc., USA
pp. 639-646
Session 4D: Parametric Variations in Design

A Model for Timing Errors in Processors with Parameter Variation (Abstract)

Brian Greskamp , University of Illinois at Urbana-Champaign, USA
Josep Torrellas , University of Illinois at Urbana-Champaign, USA
Smruti R. Sarangi , University of Illinois at Urbana-Champaign, USA
pp. 647-654

Parameter-Variation-Aware Analysis for Noise Robustness (Abstract)

Yehia Massoud , Rice University, USA
Kartik Mohanram , Rice University, USA
Mosin Mondal , Rice University, USA
pp. 655-659

Future Prediction of Self-Heating in Short Intra-Block Wires (Abstract)

Masanori Hashimoto , Osaka University, Japan
Takao Onoye , Osaka University, Japan
Kenichi Shinkai , Osaka University, Japan
pp. 660-665

Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model (Abstract)

Javid Jaffari , University of Waterloo, Canada
Mohab Anis , University of Waterloo, Canada
pp. 666-671
Luncheon Panel Discussion LP2

Do Digital Design and Variability Mix like Oil and Water? (PDF)

Clive Bittlestone , ASIC Back plane technology center, Texas Instruments
Shankar Krishnamoorthy , Sierra Design Automation
David Holt , Lightspeed Logic, Inc
Ravi Subramanian , Berkeley Design Automation
Andrew Kanhg , Blaze DFM
Michelle Clancy , Cayenne Communications
Tsuyoshi Yamamoto , Fujitsu Microelectronics America
Jacques Benkoski , Venture Executive, USVP
pp. 672-676
Session 5A: DFM Statistics

An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization (Abstract)

Long-Ching Yeh , United Microelectronics Corporation, USA
Mustafa Celik , Extreme DA Corporation, USA
Ayhan Mutlu , Extreme DA Corporation, USA
Garry Shyu , United Microelectronics Corporation, USA
Dar-sun Tsien , United Microelectronics Corporation, USA
Kelvin J. Le , Extreme DA Corporation, USA
pp. 677-684

Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy (Abstract)

Uthman Alsaiari , University of British Columbia, Canada
Resve Saleh , University of British Columbia, Canada
pp. 703-710
Session 5B: Timing Test and Reliability

Small-Delay Defect Detection in the Presence of Process Variations (Abstract)

Jacob Abraham , University of Texas at Austin, USA
Savithri Sundereswaran , Freescale Semiconductor
Rajeshwary Tayade , University of Texas at Austin, USA
pp. 711-716

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture (Abstract)

Rajsekhar Adapa , Southern Illinois University, Carbondale, USA
Hailong Cui , Qualcomm Incorporated, USA
Michael Laisne , Qualcomm Incorporated, USA
Edward Flanigan , Southern Illinois University, Carbondale, USA
Tsvetomir Petrov , Qualcomm Incorporated, USA
Spyros Tragoudas , Southern Illinois University, Carbondale, USA
pp. 717-722

On Accelerating Soft-Error Detection by Targeted Pattern Generation (Abstract)

Sandip Kundu , University of Massachusetts at Amherst, USA
Kunal Ganeshpure , University of Massachusetts at Amherst, USA
Alodeep Sanyal , University of Massachusetts at Amherst, USA
pp. 723-728

Enhanced Identification of Strong Robustly Testable Paths (Abstract)

Edward Flanigan , Southern Illinois University at Carbondale, USA
Spyros Tragoudas , Southern Illinois University at Carbondale, USA
pp. 729-736
Session 5C: Variation Analysis and Design

Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction (Abstract)

Zhuo Feng , Texas A&M University, USA
Peng Li , Texas A&M University, USA
Guo Yu , Texas A&M University, USA
pp. 737-742

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders (Abstract)

Tong Zhang , Rensselaer Polytechnic Institute
Yang Liu , Rensselaer Polytechnic Institute
Jiang Hu , Texas A&M University, USA
pp. 749-754

Designing and Validating Process-Variation-Aware Cell Libraries (Abstract)

Kayhan Kucukcakar , Synopsys, Inc., USA
Jinfeng Liu , Synopsys, Inc., USA
Sridhar Tirumala , Synopsys, Inc., USA
Ali Dasdan , Yahoo, Inc., USA
pp. 761-770
Session 5D: Lithography and OPC

Transferring Optical Proximity Correction (OPC) Effect into Optical Mode (Abstract)

Qiliang Yan , Synopsys, Inc., USA
Lawrence S. Melvin III , Synopsys, Inc., USA
Jianliang Li , Synopsys, Inc., USA
pp. 771-775

OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts (Abstract)

Tetsuya Iizuka , University of Tokyo, Japan
Makoto Ikeda , University of Tokyo, Japan
Kunihiro Asada , University of Tokyo, Japan
pp. 776-781

An Automated and Fast OPC Algorithm for OPC-Aware Layout Design (Abstract)

Xiaolang Yan , Zhejiang University, China
Ye Chen , Zhejiang University, China
Zheng Shi , Zhejiang University, China
pp. 782-787

A New Method of Implementing Hierarchical OPC (Abstract)

Yufu Zhang , Zhejiang University, China
Zheng Shi , Zhejiang University, China
pp. 788-794
Session 6A: DFM Process

A New Flexible Algorithm for Random Yield Improvement (Abstract)

Jin-Lien Lin , TSMC, Taiwan
Qing Su , Synopsys Inc., USA
Charles Chiang , Synopsys Inc., USA
Linni Wen , Synopsys Inc., USA
Frank Lee , Synopsys Inc., USA
Subarna Sinha , Synopsys Inc., USA
Yi-Kan Cheng , TSMC, Taiwan
Yu-Chyi Harn , TSMC, Taiwan
pp. 795-800

Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations (Abstract)

Yehia Massoud , Rice University, USA
Tamer Ragheb , Rice University, USA
Arthur Nieuwoudt , Rice University, USA
Hamid Nejati , Rice University, USA
pp. 801-806

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm (Abstract)

S. Ramsundar , Indian Institute of Technology, India
Dhiraj K. Pradhan , University of Bristol, United Kingdom
Ahmad Al-Yamani , KFUPM, Saudi Arabia
pp. 807-813

Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques (Abstract)

Priyanka Thakore , University of Cincinnati, USA
Ranga Vemuri , University of Cincinnati, USA
Shubhankar Basu , University of Cincinnati, USA
pp. 814-820
Session 6B: PDM Physical Planning

Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement (Abstract)

Cheng-Koh Koh , Purdue University, USA
Chen Li , Magma Design Automation, Inc., USA
pp. 829-834

Congestion Driven Buffer Planning for X-Architecture (Abstract)

Sheqin Dong , Tsinghua University, China
Hongjie Bai , Tsinghua University, China
Xianlong Hong , Tsinghua University, China
pp. 835-840

Probabilistic Congestion Prediction with Partial Blockages (Abstract)

Zhuo Li , IBM Austin, USA
Stephen T. Quay , IBM Austin, USA
Charles J. Alpert , IBM Austin, USA
Weiping Shi , Texas A&M University, USA
Sachin Sapatnekar , University of Minnesota, Minneapolis, USA
pp. 841-846

OPC-Friendly Bus Driven Floorplanning (Abstract)

Hua Xiang , IBM T.J. Watson, USA
Liang Deng , UIUC, USA
Martin D.F. Wong , UIUC, USA
Li-Da Huang , Magma Corp., USA
pp. 847-852
Session 6C: Reliability and Interconnect at the System Level

Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs (Abstract)

Frederic Worm , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
Paolo Ienne , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
Patrick Thiran , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
pp. 861-866

An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs (Abstract)

Praveen Bhojwani , Texas A&M University, USA
Rabi N. Mahapatra , Texas A&M University, USA
pp. 867-872

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations (Abstract)

Xiang Wu , AMD
Mosin Mondal , Rice University, USA
Tamer Ragheb , Rice University, USA
Yehia Massoud , Rice University, USA
Adnan Aziz , University of Texas, USA
pp. 873-878

Virtual Channels Planning for Networks-on-Chip (Abstract)

Ting-Chun Huang , Carnegie Mellon University, USA
Umit Y. Ogras , Carnegie Mellon University, USA
Radu Marculescu , Carnegie Mellon University, USA
pp. 879-884

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits (Abstract)

Vyas Krishnan , University of South Florida, USA
Srinivas Katkoori , University of South Florida, USA
pp. 885-892
Session 6D: Design and Modeling for Soft Error Reliability

MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits (Abstract)

Natasa Miskov-Zivanov , Carnegie Mellon University, USA
Diana Marculescu , Carnegie Mellon University, USA
pp. 893-898

An SEU-Tolerant Programmable Frequency Divider (Abstract)

Liang Wang , Beijing Microelectronics Technology Institute, China
Long Fan , Beijing Microelectronics Technology Institute, China
Suge Yue , Beijing Microelectronics Technology Institute, China
Yuanfu Zhao , Beijing Microelectronics Technology Institute, China
pp. 899-904

A TMR Scheme for SEU Mitigation in Scan Flip-Flops (Abstract)

Roystein Oliveira , Rutgers University, USA
Aditya Jagirdar , Rutgers University, USA
Tapan J. Chakraborty , Alcatel-Lucent, USA
pp. 905-910

Variation Impact on SER of Combinational Circuits (Abstract)

R. Rajaraman , Pennsylvania State University, USA
S. Suresh , Pennsylvania State University, USA
M.J. Irwin , Pennsylvania State University, USA
K. Ramakrishnan , Pennsylvania State University, USA
N. Vijaykrishnan , Pennsylvania State University, USA
Y. Xie , Pennsylvania State University, USA
pp. 911-916

MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments (Abstract)

Drew C. Ness , University of Minnesota, USA
Christian J. Hescott , University of Minnesota, USA
David J. Lilja , University of Minnesota, USA
pp. 917-922
Author Index

Author Index (PDF)

pp. 923-927
Best Paper Award

Best Paper Award (PDF)

pp. 929
ISQED 2008 Call for Papers
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