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Quality Electronic Design, International Symposium on (2007)
San Jose, California
Mar. 26, 2007 to Mar. 28, 2007
ISBN: 0-7695-2795-7
pp: 317-321
Dinesh Somesekhar , Intel Corporation, USA
Kaushik Roy , Purdue University, USA
Patrick Ndai , Purdue University, USA
Shih-Lien Lu , Intel Corporation, USA
ABSTRACT
We present a technique for fault tolerance in prefix-based adders, and show its application by implementing a Kogge-Stone adder. The technique is based on the fact that an n-bit Kogge-Stone adder can be split into two independent n-bit Han-Carlson (HC) adders by augmenting an additional computation stage to the adder. The presence of single faults only affects one of these HC adders, thus we use a multiplexer to select the correct output. Moreover, the adder can correct multiple faults (up to 50% faulty nodes) as long as all the faults are located on one adder. A 64-bit version of this adder is implemented, and both area & power overhead (relative to a standard KS adder) are less 20%. If faults are present, the delay is 16%. If no faults are present, the delay of the adder is 2% relative to a KS adder.
INDEX TERMS
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CITATION
Dinesh Somesekhar, Kaushik Roy, Patrick Ndai, Shih-Lien Lu, "Fine-Grained Redundancy in Adders", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 317-321, 2007, doi:10.1109/ISQED.2007.75
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