Quality Electronic Design, International Symposium on (2007)
San Jose, California
Mar. 26, 2007 to Mar. 28, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.75
Patrick Ndai , Purdue University, USA
Shih-Lien Lu , Intel Corporation, USA
Dinesh Somesekhar , Intel Corporation, USA
Kaushik Roy , Purdue University, USA
We present a technique for fault tolerance in prefix-based adders, and show its application by implementing a Kogge-Stone adder. The technique is based on the fact that an n-bit Kogge-Stone adder can be split into two independent n-bit Han-Carlson (HC) adders by augmenting an additional computation stage to the adder. The presence of single faults only affects one of these HC adders, thus we use a multiplexer to select the correct output. Moreover, the adder can correct multiple faults (up to 50% faulty nodes) as long as all the faults are located on one adder. A 64-bit version of this adder is implemented, and both area & power overhead (relative to a standard KS adder) are less 20%. If faults are present, the delay is 16%. If no faults are present, the delay of the adder is 2% relative to a KS adder.
D. Somesekhar, K. Roy, P. Ndai and S. Lu, "Fine-Grained Redundancy in Adders," 2007 IEEE International Symposium on Quality of Electronic Design(ISQED), San Jose, CA, 2007, pp. 317-321.