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Quality Electronic Design, International Symposium on (2007)
San Jose, California
Mar. 26, 2007 to Mar. 28, 2007
ISBN: 0-7695-2795-7
pp: 185-191
Minh Q. Do , Chalmers University of Technology, Sweden
Mindaugas Drazdziulis , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
Lars Bengtsson , Chalmers University of Technology, Sweden
ABSTRACT
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. Using the proposed methodology, dynamic, leakage and total power of partitioned SRAM arrays can be estimated with a 97% accuracy in comparison to the power obtained by running full circuit-level simulations.
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CITATION
Minh Q. Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson, "Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 185-191, 2007, doi:10.1109/ISQED.2007.97
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