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Quality Electronic Design, International Symposium on (2007)
San Jose, California
Mar. 26, 2007 to Mar. 28, 2007
ISBN: 0-7695-2795-7
pp: 133-138
Asha Balijepalli , Arizona State University, USA
Joseph Ervin , Arizona State University, USA
Yu Cao , Arizona State University, USA
Trevor Thornton , Arizona State University, USA
A compact model for the partially-depleted (PD) silicon-on- insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. The device has been fabricated using a standard CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried-oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180??C to 150??C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint??s Own Model (TOM3) MESFET model. A measurement-based approach is used to develop a 4-terminal device model. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also propose a wide-temperature compensation technique by source-voltage modulation.

Y. Cao, T. Thornton, J. Ervin and A. Balijepalli, "Compact Modeling of a PD SOI MESFET for Wide Temperature Designs," 2007 IEEE International Symposium on Quality of Electronic Design(ISQED), San Jose, CA, 2007, pp. 133-138.
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