The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2006)
San Jose, California
Mar. 27, 2006 to Mar. 29, 2006
ISBN: 0-7695-2523-7
TABLE OF CONTENTS
Introduction

Welcome Notes (PDF)

pp. xviii-xix
Best Paper Award

Best Paper Award (PDF)

pp. 820
Introduction
ISQED Tutorials

Tutorial 1: Emerging Technologies for VLSI Design (PDF)

Andre DeHon , California Institute of Technology, Pasadena, CA
Kaustav Banerjee , University of California, Santa Barbara, CA
Rajiv Joshi , IBM T J Watson Research Center, NY
pp. 4

Tutorial II: Variability and Its Impact on Design (PDF)

Michael Orshansky , University of Texas-Austin
Keith Bowman , Intel Corporation
Sachin S. Sapatnekar , University of Minnesota
pp. 5
ISQED Panel Discussion
ISQED Plenary Session
Session 1A: Variation Aware Timing

Variational Interconnect Delay Metrics for Statistical Timing Analysis (Abstract)

Praveen Ghanta , Arizona State University, Tempe.
Sarma Vrudhula , CSE, Arizona State University, Tempe.
pp. 19-24
Session 1A: Variation Aware Timing

Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages (Abstract)

Volkan Kursun , University of Wisconsin - Madison
Zhiyu Liu , University of Wisconsin - Madison
pp. 31-36

Constructing Current-Based Gate Models Based on Existing Timing Library (Abstract)

Bao Liu , UC San Diego, La Jolla, CA
Andrew B. Kahng , UC San Diego, La Jolla, CA
Xu Xu , UC San Diego, La Jolla, CA
pp. 37-42

Efficient Model Update for General Link-Insertion Networks (Abstract)

Peng Li , Texas A&M University
Jiang Hu , Texas A&M University
Zhuo Feng , Texas A&M University
pp. 43-50
Session 1B: High-Level Design Verification

EFSM Manipulation to Increase High-Level ATPG Effectiveness (Abstract)

Franco Fummi , Universita di Verona ,Verona, Italy
Graziano Pravadelli , Universita di Verona ,Verona, Italy
Cristina Marconcini , Universita di Verona ,Verona, Italy
Giuseppe Di Guglielmo , Universita di Verona ,Verona, Italy
pp. 57-62

A Technique for Estimating the Difficulty of a Formal Verification Problem (Abstract)

Mukul R. Prasad , Fujitsu Laboratories of America, Sunnyvale, CA, USA
Indradeep Ghosh , Fujitsu Laboratories of America, Sunnyvale, CA, USA
pp. 63-70

A Formal Verification Method of Scheduling in High-level Synthesis (Abstract)

S R Pentakota , Indian Institute of Technology, Kharagpur, India
D Sarkar , Indian Institute of Technology, Kharagpur, India
C Mandal , Indian Institute of Technology, Kharagpur, India
C Karfa , Indian Institute of Technology, Kharagpur, India
pp. 71-78
Session 1C.: Physical Planning

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction (Abstract)

Anand Rajaram , University of Texas at Austin
David Z. Pan , University of Texas at Austin
pp. 79-84

Clock Distribution Architectures: A Comparative Study (Abstract)

H. Chen , Synopsys, CA, USA
G. Wilke , UFRGS, Brazil
R. Murgai , Fujitsu Laboratories of America, Inc., CA, USA
S. Reddy , Fujitsu Laboratories of America, Inc., CA, USA
T. Miyoshi , Fujitsu Laboratories of America, Inc., CA, USA
H. Nguyen , Fujitsu Laboratories of America, Inc., CA, USA
C. Yeh , Apache Design Sol.
W. Walker , Fujitsu Laboratories of America, Inc., CA, USA
pp. 85-91

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization (Abstract)

Narender Hanchate , University of South Florida, Tampa
Nagarajan Ranganathan , University of South Florida, Tampa
pp. 92-97

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors (Abstract)

N. Vijaykrishnan , Pennsylvania State University, University Park
M. J. Irwin , Pennsylvania State University, University Park
W.-L. Hung , Pennsylvania State University, University Park
G.M. Link , Pennsylvania State University, University Park
Yuan Xie , Pennsylvania State University, University Park
pp. 98-104
ISQED Luncheon Speech
Session 2A.: Robust Device and Circuit Design

A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor (Abstract)

C. Anghel , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
A. Baguenier , 3Cadence Design Systems, France
F. Krummenacher , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
R. Gillon , AMI Semiconductor, Belgium
Y. S. Chauhan , Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
pp. 109-114

A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs (Abstract)

Yangyuan Wang , Peking University, Beijing, China
Mansun Chan , Hong Kong University of Science & Technology
Jin He , Peking University, Beijing, P.R.China
Xing Zhang , Peking University, Beijing, P.R.China
Ganggang Zhang , Peking University, Beijing, P.R.China
pp. 115-120

METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs (Abstract)

Soha Hassoun , Tufts University, Medford, MA
Brian Swahn , Tufts University, Medford, MA
pp. 121-126

A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs (Abstract)

Yangyuan Wang , Peking University, Beijing, .China
Xing Zhang , Peking University, Beijing, China
Ganggang Zhang , Peking University, Beijing, China
Jin He , Peking University, Beijing, China
pp. 127-132

Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO) (Abstract)

Sujit Dey , University of California at San Diego
Chong Zhao , University of California at San Diego
pp. 133-140
Session 2B.: Power, Noise and Timing Issues in DSM Designs

Probabilistic Delay Budgeting for Soft Realtime Applications (Abstract)

Soheil Ghiasi , University of California, Davis
Po-Kuan Huang , University of California, Davis
pp. 141-146

TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks (Abstract)

Li Ding , Synopsys, Mountain View, CA
Jindrich Zejda , Synopsys, Mountain View, CA
pp. 147-152

Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop (Abstract)

Nahmsuk Oh , Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
Alireza Kasnavi , Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
Li Ding , Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
pp. 153-159

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times (Abstract)

Ali Dasdan , Synopsys, Inc., Mountain View, CA
Kayhan Kucukcakar , Synopsys, Inc., Mountain View, CA
Emre Salman , University of Rochester
Eby G. Friedman , University of Rochester
Feroze Taraporevala , Synopsys, Inc., Mountain View, CA
pp. 159-164

Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron (Abstract)

Deniz Dal , Syracuse University
Adrian Nunez , Syracuse University
Nazanin Mansouri , Syracuse University
pp. 165-170

Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines (Abstract)

Andrew Havlir , University of Texas at Austin
David Z. Pan , University of Texas at Austin
pp. 171-178
Session 2C.: Memory Analysis

System-Level SRAM Yield Enhancement (Abstract)

Ahmed M. Eltawil , University of California, Irvine
Fadi J. Kurdahi , University of California, Irvine
Rouwaida N. Kanj , IBM Austin Research Labs
Young-Hwan Park , University of California, Irvine
Sani R. Nassif , IBM Austin Research Labs
pp. 179-184

Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model (Abstract)

Dae-Han Kim , Flash Team, SRAM/Flash Product & Technology, Samsung
Dae-Han Kim , CAE Team, Semiconductor R&D Center
Sung-Eun Yu , CAE Team, Semiconductor R&D Center
Young-Gu Kim , CAE Team, Semiconductor R&D Center
Dae-Wook Kim , CAE Team, Semiconductor R&D Center
Jae-Woo Im , Flash Team, SRAM/Flash Product & Technology, Samsung
Sang-Hoon Lee , CAE Team, Semiconductor R&D Center
Jeong-Taek Kong , CAE Team, Semiconductor R&D Center
Young-Kwan Park , CAE Team, Semiconductor R&D Center
pp. 185-189

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability (Abstract)

R. Venkatraman , LSI Logic Corporation, Milpitas, CA
S. Ramesh , LSI Logic Corporation, Milpitas, CA
R. Castagnetti , LSI Logic Corporation, Milpitas, CA
pp. 190-195

A Simulation-Based Soft Error Estimation Methodology for Computer Systems (Abstract)

Tohru Ishihara , Kyushu Univ., Fukuoka, Japan
Makoto Sugihara , ISIT, 2-1-22 Momochihama, Sawara-ku, Fukuoka, Japan
Koji Hashimoto , Fukuoka Univ.,Fukuoka, Japan
Masanori Muroyama , Kyushu Univ., Fukuoka, Japan
pp. 196-203

SRAM Local Bit Line Access Failure Analyses (Abstract)

Sani Nassif , University at Buffalo IBM Austin Research Lab
Kevin Nowka , University at Buffalo IBM Austin Research Lab
Ramalingam Sridhar , University at Buffalo IBM Austin Research Lab
Rouwaida Kanj , University at Buffalo IBM Austin Research Lab
Praveen Elakkumanan , University at Buffalo
Jente B Kuang , University at Buffalo IBM Austin Research Lab
pp. 204-209

Impact of NBTI on SRAM Read Stability and Design for Reliability (Abstract)

Chris H. Kim , University of Minnesota, Minneapolis
Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Sanjay V. Kumar , University of Minnesota, Minneapolis
pp. 210-218
Session 2D.: Posters

Minimizing FPGA Reconfiguration Data at Logic Level (Abstract)

Spyros Tragoudas , Southern Illinois University, Carbondale, IL
Haibo Wang , Southern Illinois University, Carbondale, IL
Krishna Raghuraman , Southern Illinois University, Carbondale, IL
pp. 219-224

Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques (Abstract)

Kaiping Zeng , Darmstadt University of Technology, Germany
Sorin A. Huss , Darmstadt University of Technology, Germany
pp. 225-230

Language-Based High Level Transaction Extraction on On-chip Buses (Abstract)

Yi-Le Huang , National Tsing-Hua University, China
Chun-Yao Wang , National Tsing-Hua University, China
Richard Yeh , SpringSoft, Inc., Taiwan
Yung-Chih Chen , National Tsing-Hua University, China
Shih-Chieh Chang , National Tsing-Hua University, China
pp. 231-236

Clock Skew Scheduling Under Process Variations (Abstract)

Xinjie Wei , Tsinghua University, China
Yici Cai , Tsinghua University, China
Xianlong Hong , Tsinghua University, China
pp. 237-242

A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design (Abstract)

Mesut Meterelliyoz , Purdue University, IN, USA
Qikai Chen , Purdue University, IN, USA
Kaushik Roy , Purdue University, IN, USA
pp. 243-248

Monte Carlo-Alternative Probabilistic Simulations for Analog Systems (Abstract)

Rasit Onur Topaloglu , University of California at San Diego
pp. 249-253

Process Window and Device Variations Evaluation using Array-Based Characterization Circuits (Abstract)

M. Craig , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
P. Etter , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
G. Burbach , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. Roling , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
C. Haidinyak , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
C. Tabery , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
B. Wagner , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. McGowan , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
E. Ehrichs , Advanced Micro Devices, One AMD Place, Sunnyvale, CA
pp. 260-265

Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology (Abstract)

Xiongfei Meng , University of British Columbia, Canada
Karim Arabi , MC-Sierra, Inc., BC, Canada
Resve Saleh , University of British Columbia, Canada
pp. 266-271

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming (Abstract)

X.-D Sheldon , University of California, Riverside
Yici Cai , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
I-Fan Liao , University of California, Riverside
Jeffrey Fan , University of California, Riverside
pp. 272-277

Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages (Abstract)

P. Muthana , Georgia Institute of Technology
M. Swaminathan , Georgia Institute of Technology
R. Mandrekar , Georgia Institute of Technology
K. Srinivasan , Georgia Institute of Technology
J. Choi , Georgia Institute of Technology
E. Engin , Georgia Institute of Technology
pp. 284-291

An Improved AMG-based Method for Fast Power Grid Analysis (Abstract)

Jiang Hu , Texas A&M University, College Station, TX
Kangsheng Chen , Zhejiang University, Hangzhou, China
Cheng Zhuo , Zhejiang University, Hangzhou, China
pp. 290-295

Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level (Abstract)

Arkan Abdulrahman , Southern Illinois University, Carbondale
Spyros Tragoudas , Southern Illinois University, Carbondale
pp. 300-305

Advances in Computation of the Maximum of a Set of Random Variables (Abstract)

Hai Zhou , EECS, Northwestern University, Evanston, IL
Narendra V. Shenoy , ATG, Synopsys Inc., Mountain View, CA
Debjit Sinha , EECS, Northwestern University, Evanston, IL
pp. 306-311

Leakage Biased Sleep Switch Domino Logic (Abstract)

Volkan Kursun , University of Wisconsin, Madison
Zhiyu Liu , University of Wisconsin, Madison
pp. 318-323

Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology (Abstract)

Randy Bach , LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Rich Laubhan , LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Bob Davis , LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
pp. 324-329

Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices (Abstract)

A. Stoica , Jet Propulsion Laboratory, NASA, 4800 Oak Grove Drive Pasadena, CA
T. Arslan , University of Edinburgh, Kings Buildings, Edinburgh,EH9 3JL, UK
S. Baloch , Institute for System Level Integration, Alba Centre, Alba Campus, Livingston, EH54 7EG, UK
pp. 330-345

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects (Abstract)

Jean-Marc Philippe , CEA-List DRT/DTSI/SARC/LCEI, France
S?ebastien Pillement , University of Rennes (ENSSAT), Lannion, France
Olivier Sentieys , University of Rennes (ENSSAT), Lannion, France
pp. 334-339

Processing Rate Optimization by Sequential System Floorplanning (Abstract)

Ping-Chih Wu , Cadence Design Systems Inc., San Jose, CA
Jia Wang , Northwestern University Evanston, IL
Hai Zhou , Northwestern University Evanston, IL
pp. 340-345

Fast Boolean Matching with Don?t Cares (Abstract)

A. Richard Newton , University of California at Berkeley, CA
Zile Wei , University of California at Berkeley, CA
Donald Chai , University of California at Berkeley, CA
Andreas Kuehlmann , Cadence Berkeley Labs, Berkeley, CA, USA
pp. 346-351

A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures (Abstract)

Karam S. Chatha , Arizona State University, Tempe, AZ
Krishnan Srinivasan , Arizona State University, Tempe, AZ
pp. 352-357

Core Network Interface Architecture and Latency Constrained On-Chip Communication (Abstract)

Rabi N. Mahapatra , Texas A&M University, College Station, Texas
Praveen Bhojwani , Texas A&M University, College Station, Texas
pp. 358-363

Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation (Abstract)

Vyas Krishnan , University of South Florida,Tampa
Srinivas Katkoori , University of South Florida,Tampa
pp. 364-369

Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs (Abstract)

Masahiro Fujita , University of Aizu
Takeshi Matsumoto , Electronics Engineering, University of Tokyo
Hiroshi Saito , VLSI Design and Education Center, University of Tokyo
pp. 370-375

System-level process variability compensation on memory organizations of dynamic applications: a case study (Abstract)

F. Catthoor , IMEC v.z.w, Leuven, Belgium
M. Prieto , Universidad Complutense, Madrid, Spain
C. Sanz , Universidad Complutense, 28040 Madrid, Spain
A. Papanikolaou , IMEC v.z.w, Leuven, Belgium
M. Miranda , IMEC v.z.w, Leuven, Belgium
pp. 376-382

A low input, low-power dissipation CMOS ADC (Abstract)

Lili He , San Jose State University
Biye Wang , San Jose State University
Morris Jones , San Jose State University
pp. 383-386

Constant Impedance Scaling Paradigm for Scaling LC transmission lines (Abstract)

J. Balachandran , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
G. Carchon , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
E. Beyne , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
S. Brebels , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
M. Kuijk , Vrije Universiteit Brussel,ETRO, Pleinlaan 2,1050 Brussel, Belgium
B. Nauwelaers , Katholieke Universiteit Leuven, ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium.
W.De Raedt , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
pp. 387-392

Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation (Abstract)

Hidemasa Kubota , Shizuoka University, Japan
Takayuki Watanabe , University of Shizuoka, Japan
Yuichi Tanji , Kagawa University, Japan
Hideki Asai , Shizuoka University, Japan
pp. 393-400
Session 3A.: Interconnect Analysis and Optimization

Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design (Abstract)

Yu Cao , Arizona State University
Min Chen , Arizona State University
pp. 401-406

Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk (Abstract)

Rohit Singhal , Texas A & M University, College Station, TX
Gwan S. Choi , Texas A & M University, College Station, TX
Rabi Mahapatra , Texas A & M University, College Station, TX
pp. 407-412

Compact Reduced Order Modeling for Multiple-Port Interconnects (Abstract)

Bruce McGaughy , Cadence Design Systems Inc., San Jose, CA
Lifeng Wu , Cadence Design Systems Inc., San Jose, CA
Pu Liu , University of California, Riverside
Sheldon X.-D. Tan , University of California, Riverside
pp. 413-418

Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching (Abstract)

Taeyong Je , Hanynag Univ., Ansan, Kyunggi-do, Korea
Yungseon Eo , Hanynag Univ., Ansan, Kyunggi-do, Korea
pp. 419-424

Reducing the Data Switching Activity on Serial Link Buses (Abstract)

Vivek De , Circuit Research Lab, Intel Corporation
Muhammad Khellah , Circuit Research Lab, Intel Corporation
Yehea Ismail , Northwestern University
Maged Ghoneima , Northwestern University
pp. 425-432
Session 3B: Digital Test and Diagnosis Techniques

Efficient Multiphase Test Set Embedding for Scan-based Testing (Abstract)

D. Nikolos , Computer Engineering & Informatics Dept., University of Patras, 26500 Patras, Greece
X. Kavousianos , University of Ioannina, 45110 Ioannina, Greece
E. Kalligeros , University of Ioannina, 45110 Ioannina, Greece
pp. 433-438

Evaluation of Collapsing Methods for Fault Diagnosis (Abstract)

Rajsekhar Adapa , Southern Illinois University Carbondale
Spyros Tragoudas , Southern Illinois University Carbondale
Maria K Michael , University of Cyprus
pp. 439-444

On N-Detect Pattern Set Optimization (Abstract)

Yu Huang , Mentor Graphics Corporation,
pp. 445-450

On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design (Abstract)

Hung-Ming Chen , National Chiao Tung University, Hsinchu, Taiwan
Li-Chung Hsu , SpringSoft, Inc., Hsinchu, Taiwan
pp. 451-456

An Improved Method for Identifying Linear Dependencies in Path Delay Faults (Abstract)

E. Flanigan , Southern Illinois University at Carbondale
S. Tragoudas , Southern Illinois University at Carbondale
T. Haniotakis , Southern Illinois University at Carbondale
pp. 457-462

Delay Fault Diagnosis for Non-Robust Test (Abstract)

Vishal J. Mehta , UC, Santa Barbara,CA
Malgorzata Marek-Sadowska , UC, Santa Barbara,CA
Zhiyuan Wang , Cisco Systems Inc., San Jose, CA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
pp. 463-472
Session 3C.: Back of Line DFM

Yield Improvement by Local Wiring Redundancy (Abstract)

Sven Peyer , University of Bonn, Germany
Jurgen Koehl , IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Markus Buhler , IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Dirk Muller3 , University of Bonn, Germany
Christian Schulte , University of Bonn, Germany
Jeanne Bickford , IBM Microelectronics, Burlington, VT, USA
Jason Hibbeler , IBM Microelectronics, Burlington, VT, USA
pp. 473-478

Via Distribution Model for Yield Estimation (Abstract)

Takumi Uezono , Tokyo Institute of Technology
Kazuya Masu , Tokyo Institute of Technology
Kenichi Okada , Tokyo Institute of Technology
pp. 479-484

DFM Metrics for Standard Cells (Abstract)

Robert Aitken , ARM Physical IP, Inc., Sunnyvale, CA, USA
pp. 491-496

Yield Enhancement Methodology for CMOS Standard Cells (Abstract)

Ryan Ross , Freescale Semiconductor - Crolles2 Alliance Crolles, France
Sebastien Fabre , Philips Semiconductors
Olivier Callen , STMicroelectronics
Paul Simon , Philips Semiconductors
N. Vijayaraghavan , STMicroelectronics
Matthieu Sautier , STMicroelectronics
Robin Wilson , STMicroelectronics
Arnaud Epinat , STMicroelectronics
pp. 497-502

Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask (Abstract)

Ming-Dou Ker , Institute of Electronics, National Chiao-Tung University, Taiwan
Hsin-Chyh Hsu , Institute of Electronics, National Chiao-Tung University, Taiwan
pp. 503-506
ISQED Panel Discussion 2
ISQED Plenary Session 2
Session 4A.: Analog Test and Self-Checking Design

Jitter Decomposition by Time Lag Correlation (Abstract)

Jacob A. Abraham , University of Texas at Austin
Qingqi Dou , University of Texas at Austin
pp. 525-530

Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits (Abstract)

Amit Laknaur , Southern Illinois University, Carbondale, IL
Haibo Wang , Southern Illinois University, Carbondale, IL
pp. 531-536

Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder Filters (Abstract)

C. Marques , Universidad Nacional de Cordoba, Medina Allende y Haya de Torre, Cordoba
E. Romero , Universidad Tecnologica Nacional, Argentina
J. L. Catalano , Universidad Tecnologica Nacional, Argentina
G. Peretti , Universidad Tecnologica Nacional, Argentina
pp. 543-550
Session 4B.: Power Aware Designs and Memory Management

Data Replication in Banked DRAMs for Reducing Energy Consumption (Abstract)

Mahmut Kandemir , Pennsylvania State University
Ozcan Ozturk , Pennsylvania State University
pp. 551-556

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration (Abstract)

Per Larsson-Edefors , Chalmers University of Technology, Sweden
Mindaugas Dra?zd?ziulis , Chalmers University of Technology, Sweden
Lars Bengtsson , Chalmers University of Technology, Sweden
Minh Q. Do , Chalmers University of Technology, Sweden
pp. 557-563

Accurate thermal analysis considering nonlinear thermal conductivity (Abstract)

A. Ramalingam , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX
pp. 6 pp.-649
Session 4B.: Power Aware Designs and Memory Management

Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs (Abstract)

Ozcan Ozturk , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
Sri Hari Krishna Narayanan , Pennsylvania State University
pp. 570-575

Shared Scratch-Pad Memory Space Management (Abstract)

Ozcan Ozturk , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
Ibrahim Kolcu , University of Manchester, UK
pp. 576-584
Session 4C.: Technologies for Robust Design

New Generation of Predictive Technology Model for Sub-45nm Design Exploration (Abstract)

Wei Zhao , Arizona State University, Tempe, AZ
Yu Cao , Arizona State University, Tempe, AZ
pp. 585-590

A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications (Abstract)

F. Leisenberger , Austriamicrosystems, AG
J. Payne , MEMTEL, LLC.
G. Schatzberger , Austriamicrosystems, AG
M. Thomas , MEMTEL, LLC.
E. Wachmann , Austriamicrosystems, AG
J. Pathak , MEMTEL, LLC.
M. Schrems , Austriamicrosystems, AG
A. Wiesner , Austriamicrosystems, AG
pp. 591-596

Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology (Abstract)

Tai-Xiang Lai , National Chiao-Tung University, Hsinchu, Taiw
Ming-Dou Ker , National Chiao-Tung University, Hsinchu, Taiw
pp. 597-602

Logic SER Reduction through Flipflop Redesign (Abstract)

Vivek Joshi , Indian Institute of Technology, Kanpur, India
Rajeev R. Rao , University of Michigan, Ann Arbor, MI
David Blaauw , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
pp. 611-616

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic (Abstract)

Praveen Elakkumanan , University at Buffalo
Ramalingam Sridhar , University at Buffalo
Kishan Prasad , University at Buffalo
pp. 617-624
Session 5A.: IC-Package Design Challenges

Thermal Trends in Emerging Technologies (Abstract)

G. M. Link , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
pp. 625-632

Power Gating with Multiple Sleep Modes (Abstract)

Harmander Deogun , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Kanak Agarwal , IBM Research, Austin, TX
Kevin Nowka , IBM Research, Austin, TX
pp. 633-637

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity (Abstract)

Frank Liu , IBM Research Division, Austin, TX
David Z. Pan , University of Texas, Austin, TX
Sani R. Nassif , IBM Research Division, Austin, TX
Anand Ramalingam , University of Texas, Austin, TX
pp. 644-649

Minimizing Ohmic Loss in Future Processor IR Events (Abstract)

Mark M. Budnik , Purdue University
Kaushik Roy , Purdue University
pp. 650-658
Session 5B.: IP, Interoperability: Design Optimization

A Watermarking System for IP Protection by Buffer Insertion Technique (Abstract)

Guangyu Sun , Tsinghua University, Beijing, China
Yi Xu , Tsinghua University, Beijing, China
Zhiqiang Gao , Tsinghua University, Beijing, China
pp. 671-675

Transistor-Level Optimization of Supergates (Abstract)

Themistoklis Haniotakis , Southern Illinois University, Carbondale, IL
Dimitris Kagaris , Southern Illinois University, Carbondale, IL
pp. 682-690
Session 5C.: DSM Interconnect Challenges

Study of Floating Fill Impact on Interconnect Capacitance (Abstract)

Kambiz Samadi , UCSD ECE Department, La Jolla, CA
Andrew B. Kahng , UCSD CSE and ECE Departments, La Jolla, CA
Puneet Sharma , UCSD ECE Department, La Jolla, CA
pp. 691-696

Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation (Abstract)

Fabrice Huret , LEST UMR CNRS 6165 , Brest, France
Laureline David , STMicroelectronics, France
Eric Balossier , STMicroelectronics, France
Frederic Nyer , STMicroelectronics, France
Corinne Cregut , STMicroelectronics, France
Stephane Martin , STMicroelectronics, France
pp. 703-708

A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects (Abstract)

Wenjian Yu , Tsinghua Univ., Beijing , China
Changhao Yan , Tsinghua Univ., Beijing , China
Zeyi Wang , Tsinghua Univ., Beijing , China
pp. 709-716
Session 6A.: Leakage Analysis and Optimization

LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs (Abstract)

Yu Cao , Electrical Engineering, Arizona State University, Tempe, AZ
Sarma Vrudhula , Computer Science and Engineering, Arizona State University, Tempe, AZ
Sarvesh Bhardwaj , Electrical Engineering, Arizona State University, Tempe, AZ
pp. 717-722

Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization (Abstract)

Lin Hai , Tsinghua University, Beijing, China
Luo Rong , Tsinghua University, Beijing, China
Yang Huazhong , Tsinghua University, Beijing, China
Wang Hui , Tsinghua University, Beijing, China
Wang Yu , Tsinghua University, Beijing, China
pp. 723-728

Low-leakage SRAM Design with Dual V_t Transistors (Abstract)

Behnam Amelifard , University of Southern California
Farzan Fallah , Fujitsu Labs of America, Sunnyvale, CA
Massoud Pedram , University of Southern California
pp. 729-734

Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance (Abstract)

Akhilesh Kumar , University of Waterloo, ON, Canada
Mohab Anis , University of Waterloo, ON, Canada
pp. 735-740

Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs (Abstract)

Massoud Pedram , University of Southern California
Chanseok Hwang , University of Southern California
Changwoo Kang , University of Southern California
pp. 741-746

Impact of Gate-Length Biasing on Threshold-Voltage Selection (Abstract)

Andrew B. Kahng , ECE and CSE UC San Diego
Puneet Sharma , ECE UC San Diego
Swamy Muddu , ECE UC San Diego
pp. 747-754
Session 6B.: System Level Designs and Reliability Models

FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs (Abstract)

Wei-Shen Wang , University of Texas
Bin Zhang , University of Texas
Michael Orshansky , University of Texas
pp. 755-760

Call for Papers (PDF)

pp. 821
Session 6B.: System Level Designs and Reliability Models

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC (Abstract)

V. Kalyana Chakravarty , DSP Systems, Texas Instruments, Bangalore, India.
Bhaskar J. Karmakar , DSP Systems, Texas Instruments, Bangalore, India.
R. Venkatraman , DSP Systems, Texas Instruments, Bangalore, India.
Jagdish C. Rao , DSP Systems, Texas Instruments, Bangalore, India.
pp. 769-774

Transaction Level Error Susceptibility Model for Bus Based SoC Architectures (Abstract)

N. Vijaykrishnan , Pennsylvania State University
I.-C. Lin , Pennsylvania State University
N. Dhanwada , IBM Electronic Design Automation Systems and Technology Group
S. Srinivasan , Pennsylvania State University
pp. 775-780

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC (Abstract)

Riad Ben Mouhoub , ENSTA 32, Bvd Victor, Paris, FRANCE
Omar Hammami , ENSTA 32, Bvd Victor, Paris, FRANCE
pp. 781-788
Session 6C.: Modeling for DFM

Question: DRC or DfM ? Answer: FMEA and ROI (Abstract)

Artur Balasinski , Cypress Semiconductor, San Jose, CA
pp. 789-794

Statistical Analysis of Capacitance Coupling Effects on Delay and Noise (Abstract)

Nagaraj NS , Texas Instruments Inc., Dallas, TX
Binu Abraham , Texas Instruments Inc., Dallas, TX
Usha Narasimha , Texas Instruments Inc., Dallas, TX
pp. 795-800

Bringing Manufacturing into Design via Process-Dependent SPICE Models (Abstract)

S. Krishnamurthy , Synopsys Inc, California, USA
S. Tirumala , Synopsys Inc, California, USA
X. Lin , Synopsys Inc, California, USA
D. Pramanik , Synopsys Inc, California, USA
L. Smith , Synopsys Inc, California, USA
V. Moroz , Synopsys Inc, California, USA
Y. Mahotin , Synopsys Inc, California, USA
L. Bomholt , Synopsys Inc, California, USA
pp. 801-806

Stress-Aware Design Methodology (Abstract)

Xi-Wei Lin , Synopsys, Inc., Mountain View, CA
Greg Rollins , Synopsys, Inc., Mountain View, CA
Victor Moroz , Synopsys, Inc., Mountain View, CA
Dipu Pramanik , Synopsys, Inc., Mountain View, CA
Lee Smith , Synopsys, Inc., Mountain View, CA
pp. 807-812

A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit (Abstract)

Peter Wright , Synopsys Corporation, Mountain View, CA
Minghui Fan , Synopsys Corporation, Mountain View, CA
pp. 813-817
Author Index

Author Index (PDF)

pp. 818
ISQED 2007 Call for Papers

Call for Papers (PDF)

pp. 821
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