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Quality Electronic Design, International Symposium on (2006)
San Jose, California
Mar. 27, 2006 to Mar. 29, 2006
ISBN: 0-7695-2523-7
pp: 557-563
Minh Q. Do , Chalmers University of Technology, Sweden
Mindaugas Dra?zd?ziulis , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
Lars Bengtsson , Chalmers University of Technology, Sweden
ABSTRACT
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-?m and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power.
INDEX TERMS
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CITATION
Minh Q. Do, Mindaugas Dra?zd?ziulis, Per Larsson-Edefors, Lars Bengtsson, "Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 557-563, 2006, doi:10.1109/ISQED.2006.97
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