Quality Electronic Design, International Symposium on (2006)
San Jose, California
Mar. 27, 2006 to Mar. 29, 2006
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.27
Min Chen , Arizona State University
Yu Cao , Arizona State University
Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design.
Y. Cao and M. Chen, "Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design," Proceedings of the 2006 7th International Symposium on Quality Electronic Design(ISQED), San Jose, CA, 2006, pp. 401-406.