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Quality Electronic Design, International Symposium on (2006)
San Jose, California
Mar. 27, 2006 to Mar. 29, 2006
ISBN: 0-7695-2523-7
pp: 272-277
X.-D Sheldon , University of California, Riverside
Yici Cai , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
I-Fan Liao , University of California, Riverside
Jeffrey Fan , University of California, Riverside
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain adjoint method, SLP can deliver much better quality than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for large circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase.
X.-D Sheldon, Yici Cai, Xianlong Hong, I-Fan Liao, Jeffrey Fan, "Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 272-277, 2006, doi:10.1109/ISQED.2006.81
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