The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2005)
San Jose, California
Mar. 21, 2005 to Mar. 23, 2005
ISBN: 0-7695-2301-3
TABLE OF CONTENTS

Welcome Notes (PDF)

pp. xv,xvi

Technical Subcommittees (PDF)

pp. xviii-xx
Tutorial I
Tutorial II
Session EP1
Plenary Session 1P

Shifting Perspective on DFM (PDF)

Joe Sawicki , Mentor Graphics
pp. 19
Session 1A: Tools and Flows for Quality Design

Toward Quality EDA Tools and Tool Flows Through High-Performance Computing (Abstract)

Aaron Ng , The University of Michigan
Igor L. Markov , The University of Michigan
pp. 22-27

Noise Library Characterization for Large Capacity Static Noise Analysis Tools (Abstract)

Alireza Kasnavi , Synopsys, Inc., Mountain View, CA
Sam Lo , Synopsys, Inc., Mountain View, CA
Alex Gyure , Synopsys, Inc., Mountain View, CA
William Shu , Synopsys, Inc., Mountain View, CA
Joddy W. Wang , Synopsys, Inc., Mountain View, CA
Jindrich Zedja , Synopsys, Inc., Mountain View, CA
Mahmoud Shahram , Synopsys, Inc., Mountain View, CA
Peivand F. Tehrani , Synopsys, Inc., Mountain View, CA
pp. 28-34

Two-Dimensional Layout Migration by Soft Constraint Satisfaction (Abstract)

Jianwen Zhu , University of Toronto, Canada
Qianying Tang , University of Toronto, Canada
pp. 35-39

Domain Strategy and Coverage Metric for Validation (Abstract)

Zhang Yu , Southeast University, P.R. China
Wu XuFan , Southeast University, P.R. China
Yang Jun , Southeast University, P.R. China
Luo Chun , Southeast University, P.R. China
Shi Longxing , Southeast University, P.R. China
pp. 40-45
Session 1B: High Level Power/Noise Reduction Techniques

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis (Abstract)

Yiran Chen , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Dongku Kang , Purdue University, West Lafayette, IN
pp. 48-53

Reducing Power Consumption during TLB Lookups in a PowerPC™ Embedded Processor (Abstract)

Joel Silberman , IBM Research, Yorktown Heights, NY
Shivakumar Swaminathan , IBM Microelectronics, Research Triangle Park, NC
Sanjay B. Patel , Qualcomm, Research Triangle Park, NC
James Dieffenderfer , Qualcomm, Research Triangle Park, NC
pp. 54-58

TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique (Abstract)

Chris H. Kim , University of Minnesota, Minneapolis, MN
Kee-Jong Kim , Purdue University, West Lafayette, IN; LG-Philips LCD, Korea
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 59-64

Error Analysis for the Support of Robust Voltage Scaling (Abstract)

Todd Austin , University of Michigan, USA
David Roberts , University of Michigan, USA
David Blauww , University of Michigan, USA
Kriszti?n Flautner , ARM Ltd., UK
Trevor Mudge , University of Michigan, USA
pp. 65-70
Session 1C: Leakage and Dynamic Power Issues

Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET (Abstract)

Bhavana Jharia , Indian Institute of Technology, India
R. P. Agarwal , Indian Institute of Technology, India
S. Sarkar , Indian Institute of Technology, India
pp. 72-76

Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits (Abstract)

Farzan Fallah , Fujitsu Labs of America
Afshin Abdollahi , University of Southern California
Massoud Pedram , University of Southern California
pp. 77-82

Controlled-Load Limited Switch Dynamic Logic Circuit (Abstract)

Kevin J. Nowka , IBM Austin Research Laboratory, Austin, TX
Richard B. Brown , The University of Michigan, Ann Arbor, MI
Robert K. Montoye , IBM Austin Research Laboratory, Austin, TX
Hung C. Ngo , IBM Austin Research Laboratory, Austin, TX
Jayakumaran Sivagnaname , The University of Michigan, Ann Arbor, MI
pp. 83-87

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization (Abstract)

Richard Brown , University of Utah, Salt Lake City, UT
Kevin Nowka , Austin Research Laboratories, IBM, Austin, TX
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Rahul Rao , University of Michigan, Ann Arbor, MI
Harmander Singh Deogun , University of Michigan, Ann Arbor, MI
pp. 88-93
Session 1D: Poster Session

Charge-Based Core and the Model Architecture of BSIM5 (Abstract)

Hui Wan , University of California, Berkeley, CA
Mansun Chan , University of California, Berkeley, CA
Mohan Dunga , University of California, Berkeley, CA
Ali M. Niknejad , University of California, Berkeley, CA
Chenming Hu , University of California, Berkeley, CA
Jin He , University of California, Berkeley, CA
Babak Heydari , University of California, Berkeley, CA
Jane Xi , University of California, Berkeley, CA
pp. 96-101

Integration Of Design For Manufacturability (DFM) Practices In Design Flows (Abstract)

Lionel Riviere-Cazaux , Freescale Semiconductor
Kevin Lucas , Freescale Semiconductor
Jon Fitch , Freescale Semiconductor
pp. 102-106

How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results (Abstract)

Pierluigi Daglio , STMicroelectronics, Agrate Brianza, Milan, Italy
Carlo Roma , STMicroelectronics, Agrate Brianza, Milan, Italy
Marco Pasotti , STMicroelectronics, Agrate Brianza, Milan, Italy
Marco Poles , STMicroelectronics, Agrate Brianza, Milan, Italy
Guido De Sandre , STMicroelectronics, Agrate Brianza, Milan, Italy
pp. 107-112

Leakage Current Modeling in PD SOI Circuits (Abstract)

David Blaauw , University of Michigan
Mini Nanua , Sun MicroSystems
Chanhee Oh , Nascentric Inc.
pp. 113-117

Issues and Challenges in Ramp to Production (Abstract)

Ravi Arora , Texas Instruments India
Anand Venkitachalam , Texas Instruments India
Arun Shrimali , Texas Instruments India
pp. 123-127

A Technique for Designing Totally Self-Checking Domino Logic Circuits (Abstract)

P. K. Lala , University of Arkansas, Fayetteville, AR
J. P. Parkerson , University of Arkansas, Fayetteville, AR
C. K. Tang , University of Arkansas, Fayetteville, AR
pp. 128-132

Early Assessment of Leakage Power for System Level Design (Abstract)

C. Talarico , University of Arizona, Tucson, AZ
K. L. Vakati , University of Arizona, Tucson, AZ
B. Pillilli , University of Arizona, Tucson, AZ
J. M. Wang , University of Arizona, Tucson, AZ
pp. 133-136

Technology Mapping for Reliability Enhancement in Logic Synthesis (Abstract)

Zhaojun Wo , University of Massachusetts, Amherst, MA
Israel Koren , University of Massachusetts, Amherst, MA
pp. 137-142

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays (Abstract)

Marie-Minerve Louerat , University of Paris 6, Paris, France
Andreia Cathelin , STMicroelectronics - Central R&D/DAIS, Crolles, France
Vincent Bourguet , University of Paris 6, Paris, France
DiaaEldin Khalil , Ain Shams University, Cairo, Egypt
Hani Ragai , Ain Shams University, Cairo, Egypt
Mohamed Dessouky , Ain Shams University, Cairo, Egypt
pp. 143-147

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture (Abstract)

Tetsuro Kage , Tokyo National College of Technology
Yasuaki Inoue , Waseda University
Nobuto Ono , Jedat Innovation Inc.
Hiroo Masuda , Semiconductor Technology Academic Research Center (STARC)
Atsushi Kurokawa , Semiconductor Technology Academic Research Center (STARC); Waseda University
Masaharu Yamamoto , Semiconductor Technology Academic Research Center (STARC)
pp. 153-158

Testing for Resistive Shorts in FPGA Interconnects (Abstract)

Haixia Gao , Microelectronics Institute, Xidian University, China
Xiaohua Ma , Microelectronics Institute, Xidian University, China
Yintang Yang , Microelectronics Institute, Xidian University, China
Gang Dong , Microelectronics Institute, Xidian University, China
pp. 159-163

TED Thermo Electrical Designer: A New Physical Design Verification Tool (Abstract)

E. Sokolowska , Pultronics Inc.
B. Kaminska , Pultronics Inc.
M. Barszcz , Pultronics Inc.
pp. 164-168

A Fast Lithography Verification Framework for Litho-Friendly Layout Design (Abstract)

Jeong-Taek Kong , Samsung Electronics Co., Ltd, Korea
Ki-Hung Lee , Samsung Electronics Co., Ltd, Korea
Ji-Suk Hong , Samsung Electronics Co., Ltd, Korea
Dong-Hyun Kim , Samsung Electronics Co., Ltd, Korea
Soo-Han Choi , Samsung Electronics Co., Ltd, Korea
Yong-Chan Ban , Samsung Electronics Co., Ltd, Korea
Moon-Hyun Yoo , Samsung Electronics Co., Ltd, Korea
Yoo-Hyon Kim , Samsung Electronics Co., Ltd, Korea
pp. 169-174

Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Harmander Singh Deogun , University of Michigan, Ann Arbor, MI
pp. 175-180

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer (Abstract)

Hua Xiang , IBM T.J. Watson Research Center, Yorktown Heights, NY
Martin D. F. Wong , UIUC, Urbana, IL
Kai-Yuan Chao , Intel Corporation, Hillsboro, Oregon
pp. 181-186

Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter (Abstract)

M. Pham , San Jose State University, CA
L. He , San Jose State University, CA
B. Ngo , San Jose State University, CA
J. Huynh , San Jose State University, CA
pp. 187-192

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC (Abstract)

S. Ramesh , LSI Logic Corporation, Milpitas, CA
R. Venkatraman , LSI Logic Corporation, Milpitas, CA
R. Castagnetti , LSI Logic Corporation, Milpitas, CA
T. Briscoe , LSI Logic Corporation, Milpitas, CA
A. Teene , LSI Logic Corporation, Milpitas, CA
C. Monzel , LSI Logic Corporation, Milpitas, CA
B. Bartz , LSI Logic Corporation, Milpitas, CA
pp. 193-196

Design and Evaluation of a Security Scheme for Sensor Networks (Abstract)

Themistoklis Haniotakis , Southern Illinois University Carbondale
Khadija Stewart , Southern Illinois University Carbondale
Spyros Tragoudas , Southern Illinois University Carbondale
pp. 197-201

A Minimum Cut Based Re-Synthesis Approach (Abstract)

M. Welling , Southern Illinois University at Carbondale
S. Tragoudas , Southern Illinois University at Carbondale
H. Wang , Southern Illinois University at Carbondale
pp. 202-207

Analysis for Complex Power Distribution Networks Considering Densely Populated Vias (Abstract)

Jeong-Taek Kong , Samsung Electronics Co., Ltd., Korea
Moon-Hyun Yoo , Samsung Electronics Co., Ltd., Korea
Joon-Ho Choi , Samsung Electronics Co., Ltd., Korea
Young-Seok Hong , Samsung Electronics Co., Ltd., Korea
Heeseok Lee , Samsung Electronics Co., Ltd., Korea
pp. 208-212

Buffer Planning Algorithm Based on Partial Clustered Floorplanning (Abstract)

Xianlong Hong , Tsinghua University, Beijing, China
Yuchun Ma , Tsinghua University, Beijing, China
Song Chen , Tsinghua University, Beijing, China
Sheqin Dong , Tsinghua University, Beijing, China
Chung-Kuan Cheng , University of California, San Diego
pp. 213-219
ISQED Luncheon Speech
Session 2A: Test Application and Cost Reduction

Reseeding-Based Test Set Embedding with Reduced Test Sequences (Abstract)

X. Kavousianos , University of Ioannina, Greece
D. Nikolos , University of Patras, Greece; Research Academic Computer Technology Institute, Greece
D. Kaseridis , University of Patras, Greece; Research Academic Computer Technology Institute, Greece
E. Kalligeros , University of Patras, Greece; Research Academic Computer Technology Institute, Greece
pp. 226-231

Reduced Test Application Time Based on Reachability Analysis (Abstract)

Th. Haniotakis , Southern Illinois University Carbondale
G. Pani , Southern Illinois University Carbondale
S. Tragoudas , Southern Illinois University Carbondale
pp. 232-237

Using MUXs Network to Hide Bunches of Scan Chains (Abstract)

Yinhe Han , Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Xiaowei Li , Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Yu Hu , Chinese Academy of Sciences, Beijing
Huawei Li , Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
pp. 238-243

BIST-Guided ATPG (Abstract)

Ahmad A. Al-Yamani , Stanford University, Stanford, CA; LSI Logic Corporation, Milpitas, CA
Edward J. McCluskey , Stanford University, Stanford, CA
pp. 244-249

Dynamic Test Compaction for Bridging Faults (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City, IA
pp. 250-255
Session 2B: DFM and Physical Layout

A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing (Abstract)

Charles C. Chiang , Synopsys Inc., Mountain View, CA
Xin Wang , Synopsys Inc., Mountain View, CA
Qing Su , Synopsys Inc., Mountain View, CA
Jamil Kawa , Synopsys Inc., Mountain View, CA
pp. 258-263

Performance Driven OPC for Mask Cost Reduction (Abstract)

Dennis Sylvester , University of Michigan at Ann Arbor
Andrew B. Kahng , University of California at San Diego
Jie Yang , University of Michigan at Ann Arbor
Puneet Gupta , University of California at San Diego
pp. 270-275

Meeting Nanometer DPM Requirements Through DFT (Abstract)

Jay Jahangiri , Mentor Graphics Corporation
David Abercrombie , Mentor Graphics Corporation
pp. 276-282
Session 2C: Performance and Reliability Analysis for Yield Optimization

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization (Abstract)

Dennis Sylvester , University of Michigan, Ann Arbor, MI
Anirudh Devgan , Austin Research Laboratories, IBM, Austin, TX
Kevin Nowka , Austin Research Laboratories, IBM, Austin, TX
Rahul Rao , University of Michigan, Ann Arbor, MI
Kanak Agarwal , University of Michigan, Ann Arbor, MI
Richard Brown , University of Utah, Salt Lake City, UT
pp. 284-290

Power-Delay Metrics Revisited for 90nm CMOS Technology (Abstract)

Dipanjan Sengupta , University of British Columbia, Canada
Resve Saleh , University of British Columbia, Canada
pp. 291-296

Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm (Abstract)

Justin Gregg , Colorado State University, Fort Collins
Tom W. Chen , Colorado State University, Fort Collins
pp. 297-302

Electromigration Reliability Comparison of Cu and Al Interconnects (Abstract)

Donald E. Troxel , Massachusetts Institute of Technology
Frank L. Wei , Massachusetts Institute of Technology
Chee Lip Gan , Nanyang Technological University
Syed M. Alam , Freescale Semiconductor
Carl V. Thompson , Massachusetts Institute of Technology
pp. 303-308
Session 3A: Functional Verification and Test Generation

Combining System Level Modeling with Assertion Based Verification (Abstract)

Leonid Gluhovsky , IBM Haifa Research Lab, Haifa Israel
Lyes Benalycherif , ST Microelectronics, Grenoble, France
Dmitry Pidan , IBM Haifa Research Lab, Haifa Israel
Gil Shapir , IBM Haifa Research Lab, Haifa Israel
Daniel Geist , IBM Haifa Research Lab, Haifa Israel
Younes Lahbib , ST Microelectronics, Grenoble, France
Romain Kamdem , ST Microelectronics, Grenoble, France
Anat Dahan , IBM Haifa Research Lab, Haifa Israel
Yaron Wolfsthal , IBM Haifa Research Lab, Haifa Israel
pp. 310-315

Low Voltage Test in Place of Fast Clock in DDSI Delay Test (Abstract)

Gefu Xu , Auburn University
Adit D. Singh , Auburn University
Haihua Yan , Auburn University
pp. 316-320

Functional Verification of Networked Embedded Systems (Abstract)

Franco Fummi , Universit? di Verona, Italy
Nicola Bombieri , Universit? di Verona, Italy
Graziano Pravadelli , Universit? di Verona, Italy
pp. 321-326

Functions for Quality Transition Fault Tests (Abstract)

Maria K. Michael , University of Cyprus
Spyros Tragoudas , Southern Illinois University
Stelios Neophytou , University of Cyprus
pp. 327-332
Session 3B: Power Delivery and Distribution

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems (Abstract)

Eby G. Friedman , University of Rochester, New York
Mikhail Popovich , University of Rochester, New York
pp. 334-339

Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits (Abstract)

Xiaoning Qi , Sun Microsystems Inc., Sunnyvale, CA
Navin Srivastava , University of California, Santa Barbara, CA
Kaustav Banerjee , University of California, Santa Barbara, CA
pp. 346-351

Power Grid Planning for Microprocessors and SOCS (Abstract)

David Ayers , Intel Corporation
Qing K. Zhu , Matrix Semiconductor Inc.
pp. 352-356
Session 3C: Quality System Level Design and Synthesis

A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks (Abstract)

Swarup Bhunia , Purdue University
Animesh Datta , Purdue University
Nilanjan Banerjee , Purdue University
Kaushik Roy , Purdue University
pp. 358-363

An ILP Formulation for Reliability-Oriented High-Level Synthesis (Abstract)

S. Tosun , Syracuse University
N. Mansouri , Syracuse University
Y. Xie , Pennsylvania State University
E. Arvas , Syracuse University
W-L. Hung , Pennsylvania State University
M. Kandemir , Pennsylvania State University
O. Ozturk , Pennsylvania State University
pp. 364-369

Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations (Abstract)

Yintang Yang , Xidian University, China
Xiaohua Ma , Xidian University, China
Haixia Gao , Xidian University, China
Gang Dong , Xidian University, China
pp. 370-374

Reliability-Centric Hardware/Software Co-Design (Abstract)

E. Arvas , Syracuse University
W-L. Hung , Pennsylvania State University
S. Tosun , Syracuse University
N. Mansouri , Syracuse University
M. Kandemir , Pennsylvania State University
Y. Xie , Pennsylvania State University
pp. 375-380
Session 4A: DFM for Circuit Design

Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE (Abstract)

B. Huang , University of Maryland, College Park
J. Qin , University of Maryland, College Park
M. Talmor , University of Maryland, College Park
Xiaojun Li , University of Maryland, College Park
Z. Gur , University of Maryland, College Park
Joseph B. Bernstein , University of Maryland, College Park
X. Zhang , University of Maryland, College Park
pp. 382-389

Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization (Abstract)

Henry H. Y. Chan , Microelectronics and Computer Systems Laboratory, Canada
Zeljko Zilic , Microelectronics and Computer Systems Laboratory, Canada
pp. 390-395

In-Circuit Self-Tuning of Clock Latencies (Abstract)

Chris Diorio , University of Washington, Seattle
Kambiz Rahimi , University of Washington, Seattle
pp. 396-401

Statistical Analysis of Clock Skew Variation in H-Tree Structure (Abstract)

Masanori Hashimoto , Kyoto University, Japan
Hidetoshi Onodera , Kyoto University, Japan
Tomonori Yamamoto , Kyoto University, Japan
pp. 402-407
Session 4B: Leakage and Reliability Management

Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Keunwoo Kim , IBM T. J. Watson Research Center, Yorktown Heights, NY
Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
Ching-Te Chuang , IBM T. J. Watson Research Center, Yorktown Heights, NY
Jae-Joon Kim , IBM T. J. Watson Research Center, Yorktown Heights, NY
Rajiv V. Joshi , IBM T. J. Watson Research Center, Yorktown Heights, NY
Shih-Hsien Lo , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 410-415

Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms (Abstract)

Ananth Somayaji Goda , Texas Instruments India Pvt Ltd, Bangalore, India
Gautam Kapila , Texas Instruments India Pvt Ltd, Bangalore, India
pp. 416-420

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology (Abstract)

Puneet Sharma , UCSD, La Jolla, CA
Andrew B. Kahng , Blaze DFM, Inc., Sunnyvale, CA; UCSD, La Jolla, CA
Puneet Gupta , Blaze DFM, Inc., Sunnyvale, CA
pp. 421-426

Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment (Abstract)

O. Semenov , University of Waterloo, Canada
H. Sarbishaei , University of Waterloo, Canada
M. Sachdev , University of Waterloo, Canada
pp. 427-432
Session 4C: Analog Test and BIST

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays (Abstract)

Haibo Wang , Southern Illinois University Carbondale, Carbondale, IL
Amit Laknaur , Southern Illinois University Carbondale, Carbondale, IL
pp. 434-439

A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC (Abstract)

Grazia Marchione , Politecnico di Bari, Italy
Daniela De Venuto , Politecnico di Bari, Italy
Leonardo Reyneri , Politecnico di Torino, Italy
pp. 440-447

A Built-In Self-Test Scheme for Differential Ring Oscillators (Abstract)

A. Arapoyanni , University of Athens, Greece
L. Dermentzoglou , University of Athens, Greece
Y. Tsiatouhas , University of Ioannina, Greece
pp. 448-452

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning (Abstract)

Debjyoti Ghosh , Purdue University, West Lafayette, IN
Hamid Mahmoodi , Purdue University, West Lafayette, IN
Swarup Bhunia , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 453-458
Session EP2
Plenary Session 2P

Quality and EDA (PDF)

Aki Fujimura , Cadence Design Systems, Inc.
pp. 463
Session 5A: Design Methods and Tools in DSM

ASLIC: A Low Power CMOS Analog Circuit Design Automation (Abstract)

Jihyun Lee , Northeastern University, Boston, MA
Yong-Bin Kim , Northeastern University, Boston, MA
pp. 470-475

Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models (Abstract)

Yuanzhong (Paul) Zhou , Fairchild Semiconductor, South Portland, ME
Timwah Luk , Fairchild Semiconductor, South Portland, ME
Duane Connerney , Fairchild Semiconductor, South Portland, ME
Ronald Carroll , Fairchild Semiconductor, South Portland, ME
pp. 476-481

A Mask Reuse Methodology for Reducing System-on-a-Chip Cost (Abstract)

Youngsoo Shin , Korea Advanced Institute of Science and Technology, Republic of Korea
John Darringer , IBM T.J. Watson Research Center, Yorktown Heights, NY
Subhrajit Bhattacharya , IBM T.J. Watson Research Center, Yorktown Heights, NY
Daniel Ostapko , IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 482-487
Session 5B: Design Techniques for Leakage Reduction

Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Hamid Mahmoodi , Purdue University, West Lafayette, IN
Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
pp. 490-495

Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature (Abstract)

Joseph B. Bernstein , University of Maryland, College Park, MD
Joerg D. Walter , University of Maryland, College Park, MD
Xiaojun Li , University of Maryland, College Park, MD
pp. 496-502

Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References (Abstract)

Vishal Gupta , Georgia Institute of Technology, Atlanta, GA
Gabriel A. Rinc?n-Mora , Georgia Institute of Technology, Atlanta, GA
pp. 503-508
Session 5C: Variability Issues in Nanoscale Circuits

Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS (Abstract)

Emad Hamadeh , Santa Clara University, CA; Applied Micro C. Co. (AMCC), Sunnyvale, CA
Norman Gunther , Santa Clara University, CA
Mahmud Rahman , Santa Clara University, CA
Darrell Niemann , Santa Clara University, CA
Iliya Pesic , Santa Clara University, CA; Silvaco International, Santa Clara, CA
pp. 510-515

Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization (Abstract)

Jason Cain , University of California, Berkeley, CA
Yu Cao , University of California, Berkeley, CA
Paul Friedberg , University of California, Berkeley, CA
Ruth Wang , University of California, Berkeley, CA
Jan Rabaey , University of California, Berkeley, CA
Costas Spanos , University of California, Berkeley, CA
pp. 516-521

Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations (Abstract)

Wayne Burleson , University of Massachusetts Amherst
Vishak Venkatraman , University of Massachusetts Amherst
pp. 522-527
Session 6A: Issues in Noise and Timing

A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries (Abstract)

V. Visvanathan , Texas Instruments India
Sreeram Chandrasekar , Texas Instruments India
Gaurav Kumar Varshney , Texas Instruments India
pp. 530-535

Sensitivity-Based Gate Delay Propagation in Static Timing Analysis (Abstract)

Tao Lin , Magma Design Automation, Santa Clara, CA
Massoud Pedram , University of Southern California, Los Angeles, CA
Shahin Nazarian , University of Southern California, Los Angeles, CA
Emre Tuncer , Magma Design Automation, Santa Clara, CA
pp. 536-541

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery (Abstract)

Hang Li , University of California, Riverside
Lifeng Wu , Cadence Design Systems Inc. San Jose, CA
Xianlong Hong , Tsinghua University, Beijing, China
Zhenyu Qi , University of California, Riverside
Yici Cai , Tsinghua University, Beijing, China
Sheldon X.-D. Tan , University of California, Riverside
pp. 542-547

Clock trees: differential or single ended? (Abstract)

Deepak C. Sekar , Georgia Institute of Technology, Atlanta
pp. 548-553
Session 6B: Design Approaches for System in Package (SiP)

Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP) (Abstract)

Wayne Dai , University of California, Santa Cruz
Anru Wang , University of California, Santa Cruz
pp. 562-566

This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Chung-Seok(Andy) Seo , Georgia Institute of Technology, Atlanta, GA
Nan M. Jokerst , Duke University, Durham, NC
pp. 567-572

Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach (Abstract)

Jouni Isoaho , University of Turku, Finland
Hannu Tenhunen , Royal Institute of Technology (KTH), Sweden
Esa Tjukanoff , University of Turku, Finland
Li-Rong Zheng , Royal Institute of Technology (KTH), Sweden
Meigen Shen , Royal Institute of Technology (KTH), Sweden
pp. 573-578
Session 6C: DSM Interconnect Issues

Current Calculation on VLSI Signal Interconnects (Abstract)

Li-Pen Yuan , Synopsys Inc., Mountain View, CA
Martin DF Wong , University of Illinois at Urbana-Champaign, Urbana, IL
Youxin Gao , Synopsys Inc., Mountain View, CA
Hung-Ming Chen , National Chiao Tung University, Hsinchu, Taiwan
Muzhou Shao , Synopsys Inc., Mountain View, CA
pp. 580-585

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills (Abstract)

Akira Kasebe , Meitec Corp.
Tetsuro Kage , Tokyo National College of Technology
Tetsuya Ibe , Sanyo Electric Corp.
Hiroo Masuda , STARC
Toshiki Kanamoto , Renesas Technology Corp.
Atsushi Kurokawa , STARC; Waseda University
Yasuaki Inoue , Waseda University
Chang Wei Fong , Cristal Cosmotech Corp.
pp. 586-591

Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits (Abstract)

Vinita V. Deodhar , Georgia Institute of Technology, Atlanta
Jeffrey A. Davis , Georgia Institute of Technology, Atlanta
pp. 592-597

Interconnect Delay and Slew Metrics Using the First Three Moments (Abstract)

Yun Zheng , CEC Huada Electronic Design Co., Ltd., Beijing, China
Qing Ye , Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Tianchun Ye , Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Jiaxing Sun , Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
pp. 598-602

Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits (Abstract)

Pu Liu , University of California, Riverside, CA
Zhenyu Qi , University of California, Riverside, CA
Sheldon X.-D. Tan , University of California, Riverside, CA
pp. 603-608
Session 7A: Advances in Floor Planning

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers (Abstract)

Rung-Bin Lin , Yuan Ze University, Taiwan
Meng-Chiou Wu , Yuan Ze University, Taiwan
pp. 610-615

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design (Abstract)

Xianlong Hong , Tsinghua Univ., Beijing, China
Tong Jing , Tsinghua Univ., Beijing, China
Yang Yang , Tsinghua Univ., Beijing, China
Jingyu Xu , Tsinghua Univ., Beijing, China
pp. 616-621

Best Paper Award (PDF)

pp. 707
Session 7A: Advances in Floor Planning

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning (Abstract)

Song Chen , Tsinghua Univ. China
Sheqin Dong , Tsinghua Univ. China
Chung-kuan Cheng , Univ. of California, San Diego
Yuchun Ma , Tsinghua Univ. China
Xianlong Hong , Tsinghua Univ. China
pp. 628-633

Thermal-Aware Floorplanning Using Genetic Algorithms (Abstract)

T. Theocharides , The Pennsylvania State University, University Park, PA
N. Vijaykrishnan , The Pennsylvania State University, University Park, PA
C. Addo-Quaye , The Pennsylvania State University, University Park, PA
M. J. Irwin , The Pennsylvania State University, University Park, PA
W-L. Hung , The Pennsylvania State University, University Park, PA
Y. Xie , The Pennsylvania State University, University Park, PA
pp. 634-639
Session 7B: Issues in On-Chip Communication and Analog/RF Designs

Joint Equalization and Coding for On-Chip Bus Communication (Abstract)

Srinivasa R. Sridhara , University of Illinois at Urbana Champaign
Ganesh Balamurugan , Intel Corporation, Hillsboro OR
Naresh R. Shanbhag , University of Illinois at Urbana Champaign
pp. 642-647

A More Effective C_{EFF} (Abstract)

Sani R. Nassif , IBM Austin Research Laboratory, Austin, Texas
Zhuo Li , Texas A&M University, College Station, Texas
pp. 648-653

Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter (Abstract)

Y. Koolivand , University of Tehran, Tehran, Iran
A. Zahabi , University of Tehran, Tehran, Iran
O. Shoaei , University of Tehran, Tehran, Iran
pp. 662-667

Design Considerations for Low-Power Ultra Wideband Receivers (Abstract)

Payam Heydari , University of California, Irvine
pp. 668-673
Session 7C: Robust Design under Parameter Variations

A New Method for Design of Robust Digital Circuits (Abstract)

Stephen Boyd , Stanford University, Stanford, CA
Seung-Jean Kim , Stanford University, Stanford, CA
Dinesh Patil , Stanford University, Stanford, CA
Alvin Cheung , Stanford University, Stanford, CA
Mark Horowitz , Stanford University, Stanford, CA
Sunghee Yun , Stanford University, Stanford, CA
pp. 676-681

Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction (Abstract)

Hao Yu , University of California, Los Angeles
Lei He , University of California, Los Angeles
pp. 682-687

Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations (Abstract)

Yvon Savaria , Ecole Polytechnique de Montreal, Canada
Wei Ling , Ecole Polytechnique de Montreal, Canada
pp. 688-693

Impact of Interconnect Process Variations on Memory Performance and Design (Abstract)

B. Davis , LSI Logic Corporation, Fort Collins, CO
R. Castagnetti , LSI Logic Corporation, Fort Collins, CO
J. Brown , LSI Logic Corporation, Fort Collins, CO
A. Teene , LSI Logic Corporation, Fort Collins, CO
S. Ramesh , LSI Logic Corporation, Fort Collins, CO
pp. 694-699

Author Index (PDF)

pp. 701-704
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