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Quality Electronic Design, International Symposium on (2005)
San Jose, California
Mar. 21, 2005 to Mar. 23, 2005
ISBN: 0-7695-2301-3
pp: 616-621
Xianlong Hong , Tsinghua Univ., Beijing, China
Tong Jing , Tsinghua Univ., Beijing, China
Yang Yang , Tsinghua Univ., Beijing, China
Jingyu Xu , Tsinghua Univ., Beijing, China
With System-on-Chip design, IP blocks form routing obstacles that deteriorate global interconnect delay. In this paper, we present a new approach for obstacle-avoiding rectilinear minimal delay Steiner tree (OARMDST) construction. We formalize the solving of minimum delay tree through the concept of an extended minimization function, and trade the objective into a top-down recursion, which wisely produces delay minimization from source to critical sinks. We analyze the topology generation with treatment of obstacles and exploit the connection flexibilities. To our knowledge, this is the first in-depth study of OARMDST problem based on topological construction. Experimental results are given to demonstrate the efficiency of the algorithm.
Xianlong Hong, Tong Jing, Yang Yang, Jingyu Xu, "Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 616-621, 2005, doi:10.1109/ISQED.2005.86
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