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Quality Electronic Design, International Symposium on (2005)
San Jose, California
Mar. 21, 2005 to Mar. 23, 2005
ISBN: 0-7695-2301-3
pp: 516-521
Paul Friedberg , University of California, Berkeley, CA
Yu Cao , University of California, Berkeley, CA
Jason Cain , University of California, Berkeley, CA
Ruth Wang , University of California, Berkeley, CA
Jan Rabaey , University of California, Berkeley, CA
Costas Spanos , University of California, Berkeley, CA
ABSTRACT
Within-die spatial correlation of device parameter values caused by manufacturing variations [1] has a significant impact on circuit performance. Based on experimental and simulation results, we (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact on the variability of circuit performance.
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CITATION

J. Cain, Y. Cao, P. Friedberg, R. Wang, J. Rabaey and C. Spanos, "Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization," Proceedings. 6th International Symposium on Quality Electronic Design(ISQED), San Jose, CA, USA, 2005, pp. 516-521.
doi:10.1109/ISQED.2005.82
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