Quality Electronic Design, International Symposium on (2005)
San Jose, California
Mar. 21, 2005 to Mar. 23, 2005
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.51
Syed M. Alam , Freescale Semiconductor
Frank L. Wei , Massachusetts Institute of Technology
Chee Lip Gan , Nanyang Technological University
Carl V. Thompson , Massachusetts Institute of Technology
Donald E. Troxel , Massachusetts Institute of Technology
Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the Cu and inter-level diffusion barrier, such as Si₃N₄, interface, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating condition, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.
D. E. Troxel, F. L. Wei, C. L. Gan, S. M. Alam and C. V. Thompson, "Electromigration Reliability Comparison of Cu and Al Interconnects," Proceedings. 6th International Symposium on Quality Electronic Design(ISQED), San Jose, CA, USA, 2005, pp. 303-308.