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Quality Electronic Design, International Symposium on (2005)
San Jose, California
Mar. 21, 2005 to Mar. 23, 2005
ISBN: 0-7695-2301-3
pp: 48-53
Yiran Chen , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Dongku Kang , Purdue University, West Lafayette, IN
ABSTRACT
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage, the proposed method generates schedule and resource allocation with a floorplan such that the power supply noise is minimized. To achieve the goal, we formulated the problem using a genetic algorithm. Compared to designs that do not consider supply noise, the proposed methodology reduces power supply noise up to 44%.
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CITATION
Yiran Chen, Kaushik Roy, Dongku Kang, "Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis", Quality Electronic Design, International Symposium on, vol. 00, no. , pp. 48-53, 2005, doi:10.1109/ISQED.2005.97
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