The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2004)
San Jose, California
Mar. 22, 2004 to Mar. 24, 2004
ISSN: 2003116307
ISBN: 0-7695-2093-6
TABLE OF CONTENTS

ISQED 2004 (PDF)

pp. iii
Introduction

Welcome Notes (PDF)

pp. xv-xvi
ISQED Tutorials: Compact Modeling and Analysis for Nanometer-Scale CMOS Design

null (PDF)

pp. null

Tutorial Part 1: Nanometer-Scale CMOS Devices (PDF)

Kerry Bernstein , IBM T.J. Watson Research Center
pp. 7
ISQED Panel Discussion EP1

null (PDF)

pp. null
Plenary Session I

null (PDF)

pp. null

Design for Manufacturing? Design for Yield!!! (PDF)

Marc Levitt , Cadence Design Systems, Inc.
pp. 19
Session 1A: Physical Design Migration

null (PDF)

pp. null

Calligrapher: A New Layout Migration Engine Based on Geometric Closeness (Abstract)

Fang Fang , University of Toronto
Jianwen Zhu , University of Toronto
pp. 25-30

Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design (Abstract)

Kuang-Kuo Lin , Intel Corporation
Sudhakar Kale , Intel Corporation
Aditi Nigam , Intel Corporation
pp. 31-35
Session 1B: CMOS Device and Memory

null (PDF)

pp. null

A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach (Abstract)

Chung-Hsun Lin , University of California at Berkeley
Xuemei Xi , University of California at Berkeley
Mansun Chan , Hong Kong University of Science and Technology
Jin He , University of California at Berkeley
Ali Niknejad , University of California at Berkeley
Chenming Hu , University of California at Berkeley
pp. 45-50

Leakage Increase of Narrow and Short BCPMOS (Abstract)

O. Pohland , Cypress Semiconductor
C. Cai , Cypress Semiconductor
Y. Z. Xu , Cypress Semiconductor
H. Puchner , Cypress Semiconductor
pp. 51-54

SRAM Leakage Suppression by Minimizing Standby Supply Voltage (Abstract)

Dejan Markovic , University of California at Berkeley
Jan Rabaey , University of California at Berkeley
Andrei Vladimirescu , University of California at Berkeley
Huifang Qin , University of California at Berkeley
Yu Cao , University of California at Berkeley
pp. 55-60
Session 1C: Poster Session

null (PDF)

pp. null

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling (Abstract)

Zuying Luo , Tsinghua University
Zhu Pan , Tsinghua University
Sheldon X.-D. Tan , University of California at Riverside
Yici Cai , Tsinghua University
Xianlong Hong , Tsinghua University
pp. 63-68

Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction (Abstract)

Lucanus Simonson , University of California at Los Angeles
King Ho Tam , University of California at Los Angeles
Mosur Mohan , Intel Corporation
Lei He , University of California at Los Angeles
Nataraj Akkiraju , Intel Corporation
pp. 69-74

Design for Testability of FPGA Blocks (Abstract)

Zeljko Zilic , McGill University
Stuart McCracken , Analog Devices, Inc.
pp. 86-91

Transistor Level Budgeting for Power Optimization (Abstract)

S. Ghiasi , University of California at Los Angeles
E. Kursun , University of California at Los Angeles
M. Sarrafzadeh , University of California at Los Angeles
pp. 116-121

Resistance Matrix in Crosstalk Modeling for Muliconductor Systems (Abstract)

Shoba Krishnan , Santa Clara University
Cary Y. Yang , Santa Clara University
Sunil Yu , Santa Clara University and KAIST
Kwyro Lee , KAIST
Dusan M. Petranovic , Mentor Graphics Corporation
pp. 122-125

Low Power 260 k Color TFT LCD One-Chip Driver IC (Abstract)

Soon-Yang Hong , Tomato LSI Inc.
Young-Gi Kim , Tomato LSI Inc.
Bo-Sung Kim , Tomato LSI Inc.
pp. 126-130

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids (Abstract)

David Blaauw , University Michigan
Woo Hyung Lee , University Michigan
Sanjay Pant , University Michigan
pp. 131-136

A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution Networks (Abstract)

Young-Hoe Cheon , Samsung Electronics Co., Ltd.
Joon-Ho Choi , Samsung Electronics Co., Ltd.
Jong-Eun Koo , Samsung Electronics Co., Ltd.
Moon-Hyun Yoo , Samsung Electronics Co., Ltd.
Jeong-Taek Kong , Samsung Electronics Co., Ltd.
Kyung-Ho Lee , Samsung Electronics Co., Ltd.
pp. 137-142

Rewiring for Watermarking Digital Circuits (Abstract)

Spyros Tragoudas , Southern Illinois University
M. Moiz Khan , Southern Illinois University
pp. 143-148
ISQED Luncheon Speech

null (PDF)

pp. null

The IP Quality Revolution (Abstract)

Michael Keating , Synopsys Inc.
pp. 151-155
Session 2A: Topics in Printability

null (PDF)

pp. null

A Pattern Matching System for Linking TCAD and EDA (Abstract)

Frank E. Gennari , University of California at Berkeley
Andrew R. Neureuther , University of California at Berkeley
pp. 165-170
Session 2B: Package Design and Interaction

null (PDF)

pp. null

Design Tools for Packaging (Abstract)

Anju Kapur , Intel Corporation
Lalitha Immaneni , Intel Corporation
Brett Neal , Intel Corporation
pp. 179-183

Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics (Abstract)

Li-Rong Zheng , Royal Institute of Technology
Meigen Shen , Royal Institute of Technology
Hannu Tenhunen , Royal Institute of Technology
pp. 184-189

A Clustering Based Area I/O Planning for Flip-Chip Technology (Abstract)

Janet Wang , University of Arizona at Tucson
Kishore Kumar Muchherla , University of Arizona at Tucson
Jai Ganesh Kumar , University of Arizona at Tucson
pp. 196-201
Session 2C: Test Generation and Application

null (PDF)

pp. null

Low Power Testing by Test Vector Ordering with Vector Repetition (Abstract)

M. Bellos , University of Patras and Research Academic Computer Technology Institute
X. Kavousianos , University of Ioannina
D. Nikolos , University of Patras and Research Academic Computer Technology Institute
D. Bakalis , University of Patras and Research Academic Computer Technology Institute
pp. 205-210

Test Application Time Reduction for Scan Circuits Using Limited Scan Operations (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
Yonsang Cho , Purdue University
pp. 211-216

Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming (Abstract)

H. Navarro , University of Las Palmas de Gran Canaria
Juan A. Montiel-Nelson , University of Las Palmas de Gran Canaria
José C. García , University of Las Palmas de Gran Canaria
J. Sosa , University of Las Palmas de Gran Canaria
pp. 217-222
Session 3A: Modeling and Simulations of Electromigration and Eletromagnetic Effect

null (PDF)

pp. null

A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification (Abstract)

Rajendran Panda , Motorola Inc.
Pon Ku , Motorola Inc.
Chanhee Oh , Motorola Inc.
Haldun Haznedar , Motorola Inc.
Martin Gall , Motorola Inc.
Vladimir Zolotov , Motorola Inc.
Amir Grinshpon , Motorola Inc.
pp. 232-237

Circuit Level Reliability Analysis of Cu Interconnects (Abstract)

Donald E. Troxel , Massachusetts Institute of Technology
Gan Chee Lip , Nanyang Technological University
Syed M. Alam , Massachusetts Institute of Technology
Carl V. Thompson , Massachusetts Institute of Technology
pp. 238-243

Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow (Abstract)

Daniel White , Lawrence Livermore National Laboratory
Pavel V. Nikitin , University of Washington
Yong Wang , University of Washington
C.-J. Richard Shi , University of Washington
Rob Sharpe , Lawrence Livermore National Laboratory
Vikram Jandhyala , University of Washington
John D. Rockway , Lawrence Livermore National Laboratory
Nathan Champagne , Lawrence Livermore National Laboratory
Gong Ouyang , University of Washington
John W. Rockway , Space and Naval Warfare Systems Command
Chuanyi Yang , University of Washington
pp. 244-249
Session 3B: Interconnect: Capacitance Extraction and Delay Calculation

null (PDF)

pp. null

A Divide-and-Conquer Algorithm for 3D Capacitance Extraction (Abstract)

Fangqing Yu , Texas A&M University
Weiping Shi , Texas A&M University
pp. 253-258

A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array (Abstract)

Christoph Wasshuber , Texas Instruments
Kaustav Banerjee , University of California at Santa Barbara
Anirban Basu , University of California at Santa Barbara
Adrian M. Ionescu , Swiss Federal Institute of Technology
Sheng-Chih Lin , University of California at Santa Barbara
pp. 259-264

Interconnect Mode Conversion in High-Speed VLSI Circuits (Abstract)

P.M. Martin , Universit? de Bretagne
Y. Qu?r? , Universit? de Bretagne
T. LeGouguec , Universit? de Bretagne
F. Huret , Universit? de Bretagne
pp. 265-270

Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation (Abstract)

Mei Xue , Shanghai Jiao Tong University
Ye Liu , Shanghai Jiao Tong University
Zheng-Fan Li , Shanghai Jiao Tong University
Rui-Feng Xue , Shanghai Jiao Tong University
pp. 271-275

PARADE: PARAmetric Delay Evaluation under Process Variation (Abstract)

Zhuo Li , Texas A&M University
D. M. H. Walker , Texas A&M University
Xiang Lu , Texas A&M University
Wangqi Qiu , Texas A&M University
Weiping Shi , Texas A&M University
pp. 276-280
Session 3C: Substrate Noise: Analysis and Prevention

null (PDF)

pp. null

Substrate Coupling: Modeling, Simulation and Design Perspectives (Abstract)

Edoardo Charbon , Swiss Federal Institute of Technology
Ranjit Gharpurey , University of Michigan
pp. 283-290

An Overview of Substrate Noise Reduction Techniques (Abstract)

Manoj Sachdev , University of Waterloo
Shahab Ardalan , University of Waterloo
pp. 291-296

Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs (Abstract)

Meng-Fan Chang , National Chiao Tung University
Kuei-Ann Wen , National Chiao Tung University
Ding-Ming Kwai , Intellectual Property Library Company
pp. 297-302

Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design (Abstract)

Yi-Chang Lu , Stanford University
Georgios Veronis , Stanford University
Robert W. Dutton , Stanford University
pp. 303-308
ISQED Panel Discussion EP2

null (PDF)

pp. null
Plenary Session II

null (PDF)

pp. null
Session 4A: Interconnect Delay and Coupling

null (PDF)

pp. null

A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects (Abstract)

Tom Chen , Colorado State University
Medha Kulkarni , Colorado State University
pp. 331-336

Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching (Abstract)

William R. Eisenstadt , Hanyang University
Yungseon Eo , Hanyang University
Jongin Shim , Hanyang University
Seongkyun Shin , Hanyang University
pp. 337-342

A Scalable Communication-Centric SoC Interconnect Architecture (Abstract)

Partha Pratim Pande , University of British Columbia
Cristian Grecu , University of British Columbia
Andr? Ivanov , University of British Columbia
Res Saleh , University of British Columbia
pp. 343-348
Session 4B: Analysis of Variations

null (PDF)

pp. null

Application Specific Worst Case Corners Using Response Surfaces and Statistical Models (Abstract)

Sharad Saxena , PDF Solutions
Sean Minehane , PDF Solutions
Lidia Daldoss , PDF Solutions
Glen Kramer , PDF Solutions
Jianjun Cheng , PDF Solutions
Manidip Sengupta , PDF Solutions
pp. 351-356

Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method (Abstract)

Janet Wang , University of Arizona at Tucson
Omar Hafiz , University of Arizona at Tucson
pp. 363-368
Session 4C: Layout and Design Techniques for Quality and Reliability

null (PDF)

pp. null

Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells (Abstract)

Kunihiro Asada , University of Tokyo
Makoto Ikeda , University of Tokyo
Tetsuya Iizuka , University of Tokyo
pp. 377-380

Buffered Clock Tree for High Quality IC Design (Abstract)

Jiang Hu , Texas A&M University
Rishi Chaturvedi , Texas A&M University
pp. 381-386
Session 5A: Analog Testing

null (PDF)

pp. null

A Versatile High Speed Bit Error Rate Testing Scheme (Abstract)

Yongquan Fan , McGill University
Zeljko Zilic , McGill University
Man Wah Chiang , McGill University
pp. 395-400

Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits (Abstract)

Achintya Halder , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 401-406
Session 5B: Low Power Design

null (PDF)

pp. null

Power Supply Optimization in sub-130 nm Leakage Dominant Technologies (Abstract)

Man L Mui , University of Illinois at Urbana-Champaign
Amit Mehrotra , University of Illinois at Urbana-Champaign
Kaustav Banerjee , University of California at Santa Barbara
pp. 409-414

Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates (Abstract)

Ge Yang , University of California at Santa Cruz
Zhongda Wang , University of California at Santa Cruz
Sung-Mo Kang , University of California at Santa Cruz
pp. 421-424
Session 5C: ESD

null (PDF)

pp. null

Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels (Abstract)

Wen-Yu Lo , Silicon Intergrated Systems (SiS) Corp.
Wei-Jen Chang , National Chiao-Tung University
Ming-Dou Ker , National Chiao-Tung University
pp. 433-438

Full-Chip Analysis Method of ESD Protection Network (Abstract)

Sachio Hayashi , Toshiba Corporation Semiconductor Company
Fumihiro Minami , Toshiba Corporation Semiconductor Company
Masaaki Yamada , Toshiba Microelectronics Corporation
pp. 439-444

Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes (Abstract)

Wen-Yi Chen , National Chiao-Tung University
Ming-Dou Ker , National Chiao-Tung University
pp. 445-450
Session 6A: DFM Design Techniques

null (PDF)

pp. null

Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction (Abstract)

Petros Drineas , Rensselaer Polytechnic Institute
Sobeeh Almukhaizim , Yale University
Yiorgos Makris , Yale University
pp. 459-464

Cost Model Analysis of DFT Based Fault Tolerant SOC Designs (Abstract)

Shambhu Upadhyaya , University at Buffalo
Karthik Sundararaman , University at Buffalo
Martin Margala , University of Rochester
pp. 465-469

IPQ: IP Qualification for Efficient System Design (Abstract)

Martin Radetzki , sci-worx GmbH
Hans-J? Brand , AMD Saxony LLC & Co. KG
Steffen R? , Fraunhofer Institute for Integrated Circuits/EAS, Zeunerstr
pp. 478-482
Session 6B: Delay Test Issues

null (PDF)

pp. null

Delay Fault Diagnosis Using Timing Information (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Malgorzata Marek-Sadowska , University of California at Santa Barbara
Zhiyuan Wang , University of California at Santa Barbara
Kun-Han Tsai , Mentor Graphics Corporation
pp. 485-490

An Adaptive Path Delay Fault Diagnosis Methodology (Abstract)

Saravanan Padmanaban , University of Maryland Baltimore County
Spyros Tragoudas , Southern Illinois University
pp. 491-496

Scan BIST Targeting Transition Faults Using a Markov Source (Abstract)

Hangkyu Lee , Purdue University
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 497-502

The Effect of Threshold Voltages on the Soft Error Rate (Abstract)

Y. Xie , Pennsylvania State University
R. Ramanarayanan , Pennsylvania State University
V. Degalahal , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
pp. 503-508
Session 6C: Circuit Design Trends in DSM

null (PDF)

pp. null

FinFET SRAM - Device and Circuit Design Considerations (Abstract)

Aditya Bansal , Purdue University
Kaushik Roy , Purdue University
Hari Ananthan , Purdue University
pp. 511-516

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process (Abstract)

Volkan Kursun , University of Rochester
Siva G. Narendra , Intel Corporation
Vivek K. De , Intel Corporation
Eby G. Friedman , University of Rochester
pp. 517-521

A High Performance Radiation-Hard Field Programmable Analog Array (Abstract)

Hu Huang , University of Maryland at College Park
Kuan-Jung Chung , University of Maryland at College Park
Joseph B. Bernstein , University of Maryland at College Park
J. Ari Tuchman , University of Maryland at College Park
Ji Luo , University of Maryland at College Park
Anthony L. Wilson , Mission Research Corporation
pp. 522-527

The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers (Abstract)

Ahmad Yazdi , University of California at Irvine
Payam Heydari , University of California at Irvine
pp. 528-533

An Asymmetric SRAM Cell to Lower Gate Leakage (Abstract)

Farid N. Najm , University of Toronto
Navid Azizi , University of Toronto
pp. 534-539
Backmatter

Author Index (PDF)

pp. 541-543

Best Paper Award (PDF)

pp. 547
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