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Quality Electronic Design, International Symposium on (2004)
San Jose, California
Mar. 22, 2004 to Mar. 24, 2004
ISSN: 2003116307
ISBN: 0-7695-2093-6
pp: 55-60
Huifang Qin , University of California at Berkeley
Yu Cao , University of California at Berkeley
Dejan Markovic , University of California at Berkeley
Andrei Vladimirescu , University of California at Berkeley
Jan Rabaey , University of California at Berkeley
ABSTRACT
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13µm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby VDD, with more than 90% leakage power savings.
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CITATION

D. Markovic, J. Rabaey, A. Vladimirescu, H. Qin and Y. Cao, "SRAM Leakage Suppression by Minimizing Standby Supply Voltage," Proceedings. 5th International Symposium on Quality Electronic Design(ISQED), San Jose, CA, USA, 2004, pp. 55-60.
doi:10.1109/ISQED.2004.1283650
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