The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2003)
San Jose, California
Mar. 24, 2003 to Mar. 26, 2003
ISBN: 0-7695-1881-8
TABLE OF CONTENTS

Welcome Notes (PDF)

pp. xv
ISQED TUTORIALS

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pp. null
Tutorial Track A: Design for Yield Optimization and Test

null (PDF)

pp. null
Tutorial Track B: Design for Manufacturing and Yield

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pp. null
Tutorial Track C: IC and Package Co-Design

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pp. null
Tutorial Track D: Design for Reliability

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pp. null
Plenary Session I

null (PDF)

pp. null
Session 1A: Reliability and Design in Deep Submicron Technologies

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pp. null

Reliability Evaluation for Integrated Circuit with Defective Interconnect under Electromigration (Abstract)

Xiangdong Xuan , Georgia Institute of Technology
Adit D. Singh , Auburn University
Abhijit Chatterjee , Georgia Institute of Technology
pp. 29

Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs (Abstract)

Amir H. Ajami , University of Southern California
Amit Mehrotra , University of Illinois at Urbana-Champaign
Kaustav Banerjee , University of California at Santa Barbara
Massoud Pedram , University of Southern California
pp. 35

Random Sampling for On-Chip Characterization of Standard-Cell Propagation Delay (Abstract)

L. Croce , University of Urbino
S. Maggioni , STMicroelectronics
A. Bogliolo , University of Urbino
A. Veggetti , STMicroelectronics
pp. 41
Session 1B: Reducing Leakage Currents in VLSI Circuits

null (PDF)

pp. null

Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains (Abstract)

Massoud Pedram , University of Southern California
Afshin Abdollahi , University of Southern California
Farzan Fallah , Fujitsu Laboratories of America
pp. 49

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic (Abstract)

Tom Chen , Colorado State University
Geun Rae Cho , Colorado State University
pp. 55

Design Techniques for Gate-Leakage Reduction in CMOS Circuits (Abstract)

Rafik S. Guindi , University of Toronto
Farid N. Najm , University of Toronto
pp. 61
Session 1C: SoC Methodology

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pp. null

True Coverage:A Goal of Verification (Abstract)

Gary Feierbach , Apple Computer, Inc.
Vijay Gupta , Apple Computer, Inc.
pp. 75

Low-Cost and Real-Time Super-Resolution over a Video Encoder IP (Abstract)

Ramanathan Sethuraman , Philips Research Laboratories Eindhoven
Rafael Peset Llopis , Philips Consumers Electronics
Gustavo M. Callicó , Applied Microelectronics Research Institute
Antonio Núñez , Applied Microelectronics Research Institute
pp. 79
Session 2A: Testing of SoCs

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pp. null

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets (Abstract)

Nilanjan Mukherjee , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa
Yu Huang , Mentor Graphics Corporation
Chien-Chung Tsai , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
pp. 99
Session 2B: Design for Manufacturability and Quality

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pp. null

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability (Abstract)

O. Kobozeva , LSI Logic Corporation
F. Duan , LSI Logic Corporation
R. Venkatraman , LSI Logic Corporation
R. Castagnetti , LSI Logic Corporation
S. Ramesh , LSI Logic Corporation
pp. 119

New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains (Abstract)

David Pinto , Numerical Technologies
Pradiptya Ghosh , Numerical Technologies
Chung-shin Kang , Numerical Technologies
Michael Sanie , Numerical Technologies
pp. 131

System and Framework for QA of Process Design Kits (Abstract)

J. D. Carothers , University of Arizona
M. C. Scott , Texas Instruments
M. O. Peralta , Texas Instruments
pp. 138

The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange (Abstract)

Gilles-Eric Descamps , Silicon Access Networks
Sridhar Subramaniam , Silicon Access Networks
Subramanian Ganesan , Silicon Access Networks
Satish Bagalkotkar , Silicon Access Networks
Hem Hingarh , Silicon Access Networks
pp. 144
Session 2C: Invited Papers Session-Design Considerations in Advanced Technology

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pp. null

Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits (Abstract)

R. Puri , IBM T. J. Watson Research Center
C. T. Chuang , IBM T. J. Watson Research Center
R. V. Joshi , IBM T. J. Watson Research Center
K. Kim , IBM T. J. Watson Research Center
pp. 153

Revisiting the Noise Figure Design Metric for Digital Communication Receiver (Abstract)

Won Namgoong , University of Southern California
Jongrit Lerdworatawee , University of Southern California
pp. 159

Benchmarks for Interconnect Parasitic Resistance and Capacitance (Abstract)

Poras Balsara , University of Texas at Dallas
Abha Singh , Texas Instruments Inc.
Usha Narasimha , Texas Instruments Inc.
Mak Kulkarni , Texas Instruments Inc.
Frank Cano , Texas Instruments Inc.
Cyrus Cantrell , University of Texas at Dallas
Tom Bonifield , Texas Instruments Inc.
Nagaraj NS , Texas Instruments Inc.
pp. 163
Session 3A: Interconnect and Substrate Noise

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pp. null

Post-Route Gate Sizing for Crosstalk Noise Reduction (Abstract)

Ilan Algor , Motorola Inc.
Ibrahim N. Hajj , Univ. of Illinois Urbana-Champaign
Chanhee Oh , Motorola Inc.
Murat R. Becer , Motorola Inc.
Vladimir Zolotov , Motorola Inc.
Rajendran Panda , Motorola Inc.
David Blaauw , Univ. of Michigan Ann Arbor
pp. 171

Noise-Aware Driver Modeling for Nanometer Technology (Abstract)

P. V. Srinivas , University of California, San Diego
Sujit Dey , University of California, San Diego
Xiaoliang Bai , University of California, San Diego
Rajit Chandra , University of California, San Diego
pp. 177

Modeling Crosstalk Induced Delay (Abstract)

Malgorzata Marek-Sadowska , University of California, Santa Barbara
Chung-Kuan Tsai , University of California, Santa Barbara
pp. 189
Session 3B: Impact of New Standards for Design Data Modeling and Manufacturing Interface

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pp. null

Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint (Abstract)

Igor L. Markov , The University of Michigan
Andrew B. Kahng , University of California, San Diego
pp. 208
Session 3C: Package-Design Interface Challenges

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pp. null

Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform (Abstract)

Michael Wang , University of California, Santa Cruz
Katsuharu Suzuki , University of California, Santa Cruz
Wayne Dai , University of California, Santa Cruz
pp. 229

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC (Abstract)

Hsin-Chin Jiang , Industrial Technology Research Institute
Ming-Dou Ker , National Chiao-Tung University
Jeng-Jie Peng , Industrial Technology Research Institute
pp. 241
Evening Panel Discussion: IC and Package Co-Design: Challenge or Dream?

IC & Package Co-Design: Challenge or Dream? (Abstract)

Soroush Abbaspour , University of Southern California
Massoud Pedram , University of Southern California
Payam Heydari , University of California, Irvine
pp. 247
Plenary Session II

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pp. null
Session 4A: Power Analysis and Low Power Design

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pp. null

Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers (Abstract)

Massoud Pedram , University of Southern California
Payam Heydari , University of California, Irvine
Soroush Abbaspour , University of Southern California
pp. 261

Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs (Abstract)

Hyung Gyu Lee , Seoul National University
Sungyuep Nam , Seoul National University
Naehyuck Chang , Seoul National University
pp. 267

MONOLITHIC DC-DC CONVERTER ANALYSIS AND MOSFET GATE VOLTAGE OPTIMIZATION (Abstract)

Volkan Kursun , University of Rochester
Eby G. Friedman , University of Rochester
Siva G. Narendra , Intel Corporation
Vivek K. De , Intel Corporation
pp. 279
Session 4B: Topics in Device and Interconnect Modeling

null (PDF)

pp. null

Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design (Abstract)

Dongwoo Lee , University of Michigan
Wesley Kwong , University of Michigan
Dennis Sylvester , University of Michigan
David Blaauw , University of Michigan
pp. 287

Design and Analysis of Low-Voltage Current-Mode Logic Buffers (Abstract)

Payam Heydari , University of California, Irvine
pp. 293

Reduced-Order Modeling Based on PRONY?s and SHANK?s Methods via the Bilinear Transformation (Abstract)

Amit Mehrotra , University of Illinois at Urbana-Champaign
Makram M. Mansour , University of Illinois at Urbana-Champaign
pp. 299
Session 4C: Techniques for High-Speed Circuits and Module Generation

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pp. null

A Novel Clocking Strategy for Dynamic Circuits (Abstract)

Yong-Bin Kim , Northeastern University
Jong-Jin Lim , Northeastern University
Young Jun Lee , Northeastern University
pp. 307

Procedural Analog Design (PAD) Tool (Abstract)

Maher Kayal , Swiss Federal Institute of Technology, Electronics Labs
Vanco B. Litovski , University of Nis
Marc Pastre , Swiss Federal Institute of Technology, Electronics Labs
Danica Stefanovic , Swiss Federal Institute of Technology, Electronics Labs; University of Nis
pp. 313

Parameterized Macrocells with Accurate Delay Models for Core-Based Designs (Abstract)

Mohammad M. Mansour , University of Illinois at Urbana-Champaign
Makram M. Mansour , University of Illinois at Urbana-Champaign
Amit Mehrotra , University of Illinois at Urbana-Champaign
pp. 319
Session 5A: Timing and Noise Issues in Physical Design

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pp. null

Minimizing Inter-Clock Coupling Jitter (Abstract)

Sao-Jie Chen , National Taiwan University
Ming-Fu Hsiao , National Taiwan University
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 333

A Proposal for Routing-Based Timing-Driven Scan Chain Ordering (Abstract)

Stefanus Mantik , Cadence Design Systems, Inc.
Andrew B. Kahng , UC San Diego
Puneet Gupta , UC San Diego
pp. 339

Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis (Abstract)

Jae-Seok Yang , Samsung Electronics
Jeong-Taek Kong , Samsung Electronics
Moon-Hyun Yoo , Samsung Electronics
Jeong-Yeol Kim , Samsung Electronics
Joon-Ho Choi , Samsung Electronics
pp. 344

PDL: A New Physical Synthesis Methodology (Abstract)

Kazuhiro Emi , Fujitsu LSI Technology LTD.
Rajeev Murgai , Fujitsu Laboratories of America, Inc.
Kaoru Kawamura , Fujitsu Laboratories LTD.
Toshiyuki Shibuya , Fujitsu Laboratories LTD.
Tadashi Konno , Fujitsu LTD.
pp. 348
Session 5B: Reliabililty Analysis

null (PDF)

pp. null

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits (Abstract)

Jeng-Jie Peng , Industrial Technology Research Institute
Hsin-Chyh Hsu , National Chiao-Tung University
Ming-Dou Ker , National Chiao-Tung University
pp. 363

Coupled Simulation of Circuit and Piezoelectric Laminates (Abstract)

Kartikeya Mayaram , Oregon State University
Cheng-gang Xu , Oregon State University
Terri Fiez , Oregon State University
pp. 369

Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling (Abstract)

Keun-Ho Lee , SAMSUNG Electronics Co., Ltd
Tae-Kyung Kim , SAMSUNG Electronics Co., Ltd
Jeong-Taek Kong , SAMSUNG Electronics Co., Ltd
Young-Kwan Park , SAMSUNG Electronics Co., Ltd
Won-Seok Lee , SAMSUNG Electronics Co., Ltd
Jin-Kyu Park , SAMSUNG Electronics Co., Ltd
pp. 373

Static Electromigration Analysis for Signal Interconnects (Abstract)

Vladimir Zolotov , Motorola, Inc
Rajendran Panda , Motorola, Inc
David Blaauw , University of Michigan
Murat Becer , Motorola, Inc
Chanhee Oh , Motorola, Inc
pp. 377
Session 5C: Panel Discussion: Hidden Quality, Crouching Customer-How Much Does the Quality of EDA Tools Impact Electronic Design?
Session 6A: Interconnect Parasitic Effects

null (PDF)

pp. null

On-Chip Interconnect Inductance - Friend or Foe (Invited) (Abstract)

Patrick Yue , Stanford University
Frank O?Mahony , Stanford University
S. Simon Wong , Stanford University
So-Young Kim , Stanford University
Bendik Kleveland , Stanford University
Richard Chang , Stanford University
pp. 389

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay (Abstract)

Takashi Sato , Hitachi, Ltd. and Kyoto University
Hiroo Masuda , Semiconductor Technology Academic Research Center
pp. 395

Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow (Abstract)

Payman Zarkesh-Ha , LSI Logic Corporation
S. Lakshminarayann , LSI Logic Corporation
William Loh , LSI Logic Corporation
Peter Wright , LSI Logic Corporation
Ken Doniger , LSI Logic Corporation
pp. 405

Analyzing Internal-Switching Induced Simultaneous Switching Noise (Abstract)

Li Yang , University of Central Florida
J. S. Yuan , University of Central Florida
pp. 410
Session 6B: Design and Measurement Issues in Testing

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pp. null

Generation of Hazard Identification Functions (Abstract)

Maria K. Michael , University of Notre Dame
Spyros Tragoudas , Southern Illinois University
pp. 419

On Structural vs. Functional Testing for Delay Faults (Abstract)

Angela Krstic , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Jing-Jia Liou , National Tsing Hua University
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
pp. 438

An Embedded I<sub>DDQ</sub> Testing Architecture and Technique (Abstract)

A. Arapoyanni , University of Athens
Y. Tsiatouhas , University of Ioannina
Th. Haniotakis , Southern Illinois Univ.
pp. 442

Author's Index (PDF)

pp. 447

Best Paper Award (PDF)

pp. 453
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